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Electrical Engineering homework help

Assignment 1

Social Media Data Collection

Review Details

Take a moment to review the details of this assignment below and gather any necessary files. Once you’re ready to submit your assignment, move on to Step 2.

Assessment Description

The purpose of this assignment is to identify social media data collection strategies and the legal and ethical issues associated with social media data mining. 


Part 1

Conduct research to identify how business organizations mine social media to collect data so they can obtain a competitive advantage in the marketplace. Locate examples of several strategies and companies. You cannot use examples already referenced in the topic Resources. Research the legal and ethical issues that are associated with data mining activities, including specific laws that govern data mining and examples of companies that have faced legal issues and negative consequences as a result of ethical issues resulting from the data mining strategies they employed.

Create a PowerPoint presentation (minimum of eight content slides) that summarizes your findings and addresses the following. Include a reference slide at the end of the presentation. 

1. Describe strategies business organizations use to mine social media to collect data and provide supporting examples.

2. Discuss how the data that are mined via social media can be used to create a competitive advantage for the business organizations.

3. Describe legal issues associated with business data mining activities, including specific laws governing data mining practices.

4. Provide an example of a company that faced legal issues as a result of the data mining strategies it employed.

5. Discuss ethical issues associated with business data mining activities.

6. Provide an example of a company that faced negative consequences as a result of ethical issues resulting from the data mining strategies it employed.


Part 2

Practice delivering your PowerPoint. Using Loom, record your delivery of the PowerPoint presentation. Refer to the topic Resources for additional guidance on recording your presentation with Loom. Employ the following public speaking strategies: 

1. Speak slowly and clearly.

2. Make eye contact.

3. Present yourself in a professional manner.

4. Make sure that you are visible in the video.


General Requirements

Refer to the resource, “Creating Effective PowerPoint Presentations,” located in the Student Success Center, for additional guidance on completing this assignment in the appropriate style.

Submit the PowerPoint presentation file with the link to the Loom video presentation as the last reference in the references list slide. Do not try to upload the video file: It will be too big and will not upload. Do not submit any other file format, such as an Adobe PDF file, or you will not earn full credit.

While APA style is not required for the body of this assignment, solid academic writing is expected, and documentation of sources should be presented using APA formatting guidelines, which can be found in the APA Style Guide, located in the Student Success Center.

This assignment uses a rubric. Please review the rubric prior to beginning the assignment to become familiar with the expectations for successful completion.

You are not required to submit this assignment to LopesWrite.

Rubric

Collapse All RubricCollapse All

collapse Data Mining Strategies assessment

Data Mining Strategies

16.5 points

Criteria Description

Data Mining Strategies

5. Excellent

16.5 points

Descriptions and examples of strategies business organizations use to mine social media to collect data are thorough and include substantial relevant supporting details.

4. Good

14.03 points

Descriptions and examples of strategies business organizations use to mine social media to collect data are complete and include relevant supporting details.

3. Satisfactory

12.38 points

Descriptions and examples of strategies business organizations use to mine social media to collect data are included but lack relevant supporting details.

2. Less Than Satisfactory

10.73 points

Descriptions and examples of strategies business organizations use to mine social media to collect data are incomplete or incorrect.

1. Unsatisfactory

0 points

Descriptions and examples of strategies business organizations use to mine social media to collect data are not included.

collapse Competitive Advantage assessment

Competitive Advantage

16.5 points

Criteria Description

Competitive Advantage

5. Excellent

16.5 points

Discussion of how data mined via social media can be used to create a competitive advantage is thorough and contains substantial relevant supporting details.

4. Good

14.03 points

Discussion of how data mined via social media can be used to create a competitive advantage is complete and contains relevant supporting details.

3. Satisfactory

12.38 points

Discussion of how data mined via social media can be used to create a competitive advantage is incomplete or incorrect.

2. Less Than Satisfactory

10.73 points

Discussion of how data mined via social media can be used to create a competitive advantage is incomplete or incorrect.

1. Unsatisfactory

0 points

Discussion of how data mined via social media can be used to create a competitive advantage is not included.

collapse Legal Issues and Example assessment

Legal Issues and Example

16.5 points

Criteria Description

Legal Issues and Example

5. Excellent

16.5 points

Description of legal issues associated with business data mining activities (including laws governing data mining processes) and an example of a company that faced legal issues as a result of data mining strategies it employed are thorough and include substantial explanation and relevant supporting details.

4. Good

14.03 points

Description of legal issues associated with business data mining activities (including laws governing data mining processes) and an example of a company that faced legal issues as a result of data mining strategies it employed are complete and include explanation and relevant supporting details.

3. Satisfactory

12.38 points

Description of legal issues associated with business data mining activities (including laws governing data mining processes) and an example of a company that faced legal issues as a result of data mining strategies it employed are included but lack relevant supporting details.

2. Less Than Satisfactory

10.73 points

Description of legal issues associated with business data mining activities (including laws governing data mining processes) and an example of a company that faced legal issues as a result of data mining strategies it employed are incomplete or incorrect.

1. Unsatisfactory

0 points

Description of legal issues associated with business data mining activities (including laws governing data mining processes) and an example of a company that faced legal issues as a result of data mining strategies it employed are not included.

collapse Ethical Issues and Example assessment

Ethical Issues and Example

16.5 points

Criteria Description

Ethical Issues and Example

5. Excellent

16.5 points

Description of ethical issues associated with business data mining activities and an example of a company that faced negative consequences associated with ethical issues that resulted from the data mining strategies it employed are thorough and include substantial explanation and relevant supporting details.

4. Good

14.03 points

Description of ethical issues associated with business data mining activities and an example of a company that faced negative consequences associated with ethical issues that resulted from the data mining strategies it employed are complete and include explanation and relevant supporting details.

3. Satisfactory

12.38 points

Description of ethical issues associated with business data mining activities and an example of a company that faced negative consequences associated with ethical issues that resulted from the data mining strategies it employed are included but lack explanation and relevant supporting details.

2. Less Than Satisfactory

10.73 points

Description of ethical issues associated with business data mining activities and an example of a company that faced negative consequences associated with ethical issues that resulted from the data mining strategies it employed are incomplete or incorrect.

1. Unsatisfactory

0 points

Description of ethical issues associated with business data mining activities and an example of a company that faced negative consequences associated with ethical issues that resulted from the data mining strategies it employed are not included.

collapse Presentation Skills assessment

Presentation Skills

22 points

Criteria Description

Presentation Skills

5. Excellent

22 points

Student demonstrates exemplary presentation skills, including professional physical appearance and business attire, body language, eye contract, evidence of preparation, clear articulation, and adherence to 3-5 minute time limit.

4. Good

18.7 points

Student demonstrates solid presentation skills, including professional physical appearance and business attire, body language, eye contract, evidence of preparation, clear articulation, and adherence to 3-5 minute time limit.

3. Satisfactory

16.5 points

Student demonstrates moderate presentation skills, including professional physical appearance and business attire, body language, eye contract, evidence of preparation, clear articulation, and adherence to 3-5 minute time limit.

2. Less Than Satisfactory

14.3 points

Student demonstrates minimal presentation skills, including professional physical appearance and business attire, body language, eye contract, evidence of preparation, clear articulation, and adherence to 3-5 minute time limit.

1. Unsatisfactory

0 points

Student does not demonstrate presentation skills, including professional physical appearance and business attire, body language, eye contract, evidence of preparation, clear articulation, and adherence to 3-5 minute time limit.

collapse Presentation of Content assessment

Presentation of Content

5.5 points

Criteria Description

Presentation of Content

5. Excellent

5.5 points

The content is written clearly and concisely. Ideas universally progress and relate to each other. The project includes motivating questions and advanced organizers. The project gives the audience a clear sense of the main idea. Persuasive, authoritative information from reliable, credible sources is included.

4. Good

4.68 points

The content is written with a logical progression of ideas and supporting information exhibiting a unity, coherence, and cohesiveness. Persuasive information is included from reliable sources.

3. Satisfactory

4.13 points

The presentation slides are generally competent, but ideas may show some inconsistency in organization or in their relationships to each other. Some persuasive information is included.

2. Less Than Satisfactory

3.58 points

The content is vague in conveying a point of view and does not create a strong sense of purpose. Some persuasive information from reliable sources is included. Some persuasive information is included but may be unreliable or lack credibility.

1. Unsatisfactory

0 points

The content lacks a clear point of view and logical sequence of information is unclear. Little or no persuasive information from reliable sources is included.

collapse Layout assessment

Layout

5.5 points

Criteria Description

Layout

5. Excellent

5.5 points

The layout is visually pleasing and contributes to the overall message with appropriate use of headings, subheadings, and white space. Text is appropriate in length for the target audience and to the point. The background and colors enhance the readability of the text.

4. Good

4.68 points

The layout background and text complement each other and enable the content to be easily read. The fonts are easy to read and point size varies appropriately for headings and text.

3. Satisfactory

4.13 points

The layout uses horizontal and vertical white space appropriately. Sometimes the fonts are easy to read, but in a few places the use of fonts, italics, bold, long paragraphs, color, or busy background detracts and does not enhance readability.

2. Less Than Satisfactory

3.58 points

The layout shows some structure but appears cluttered and busy or distracting with large gaps of white space or a distracting background. Overall readability is difficult due to lengthy paragraphs, too many different fonts, dark or busy background, overuse of bold, or lack of appropriate indentations of text.

1. Unsatisfactory

0 points

The layout is cluttered, confusing, and does not use spacing, headings, and subheadings to enhance the readability. The text is extremely difficult to read with long blocks of text, small point size for fonts, and inappropriate contrasting colors. Poor use of headings, subheadings, indentations, or bold formatting is evident.

collapse Mechanics of Writing (includes spelling, punctuation, grammar, language use) assessment

Mechanics of Writing (includes spelling, punctuation, grammar, language use)

5.5 points

Criteria Description

Mechanics of Writing (includes spelling, punctuation, grammar, language use)

5. Excellent

5.5 points

Writer is clearly in control of standard, written academic English.

4. Good

4.68 points

Document is largely free of mechanical errors, although a few may be present.

3. Satisfactory

4.13 points

Some mechanical errors or typos are present, but they are not overly distracting to the reader.

2. Less Than Satisfactory

3.58 points

Frequent and repetitive mechanical errors distract the reader.

1. Unsatisfactory

0 points

Errors are pervasive enough that they impede communication of meaning.

collapse Documentation of Sources assessment

Documentation of Sources

5.5 points

Criteria Description

Documentation of Sources (citations, footnotes, references, bibliography, etc., as appropriate to assignment and style)

5. Excellent

5.5 points

Sources are completely and correctly documented, as appropriate to assignment and style, and format is free of error.

4. Good

4.68 points

Sources are documented, as appropriate to assignment and style, and format is mostly correct.

3. Satisfactory

4.13 points

Sources are documented, as appropriate to assignment and style, although some formatting errors may be present.

2. Less Than Satisfactory

3.58 points

Documentation of sources is inconsistent or incorrect, as appropriate to assignment and style, with numerous formatting errors.

1. Unsatisfactory

0 points

Sources are not documented

Assignment 2

Benchmark – Applying Emerging Technology in Business

Review Details

Take a moment to review the details of this assignment below and gather any necessary files. Once you’re ready to submit your assignment, move on to Step 2.

Assessment Traits

Benchmark

Assessment Description

The purpose of this assignment is to explore emerging technologies that were discussed in class that are used in business enterprises.

The following emerging technologies were discussed during this course: 

1. Blockchain

2. Artificial Intelligence (AI)

3. Augmented Reality (AR)

4. Machine Learning

5. Cognitive Computing

Choose three emerging technologies from the list above that you think will further change the way companies will conduct business over the next 10 years.

In a Microsoft Excel spreadsheet, create a table that summarizes the following information. When creating the chart, be sure to include a title and proper labels on rows and columns to ensure that readers can understand the information being presented.

1. Name of each emerging technology (NOTE: apps, social media, or devices are not emerging technology; emerging technologies are ones discussed in DQ 1).

2. Description of the role of the technology and how it correlates to information systems.

3. Description of how the technology could change business operations.

4. Description of how the technology could change the way employees work.

5. Description of how the technology could change customer interaction or the customer experience.

6. Description of how the technology could help business organizations gain competitive advantage.

7. Description of how the technology could help the organization meet goals more quickly or efficiently.

8. Documentation of resources used to learn about each technology.

Submit the Microsoft Excel spreadsheet only. Do not submit any other file format, such as an Adobe PDF file, or you will not earn full credit.

While APA style is not required for the body of this assignment, solid academic writing is expected, and documentation of sources should be presented using APA formatting guidelines, which can be found in the APA Style Guide, located in the Student Success Center.

This assignment uses a rubric. Please review the rubric prior to beginning the assignment to become familiar with the expectations for successful completion.

You are not required to submit this assignment to LopesWrite.


Benchmark Information

This benchmark assignment assesses the following programmatic competencies:

BS Business for Secondary Education

7.2: Explain the role of information technology and systems within business enterprises.

Rubric

Collapse All RubricCollapse All

collapse Name of Emerging Technology assessment

Name of Emerging Technology

22 points

Criteria Description

Name of Emerging Technology

5. 5: Excellent

22 points

The names of each emerging technology are complete and correct.

4. 4: Good

18.7 points

The names of each emerging technology are complete and correct.

3. 3: Satisfactory

16.5 points

The names of emerging technology are somewhat complete and correct. Some minor details are missing.

2. 2: Less Than Satisfactory

14.3 points

The names of each emerging technology are incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Chart does not include the name of each emerging technology.

collapse Role of Technology and information systems (C7.2) assessment

Role of Technology and information systems (C7.2)

22 points

Criteria Description

Role of Technology and information systems (C7.2)

5. 5: Excellent

22 points

Chart content describing the role of each emerging technology and how it correlates to information systems is thorough and includes substantial relevant supporting details.

4. 4: Good

18.7 points

Chart content describing the role of each emerging technology and how it correlates to information systems is complete and includes relevant supporting details.

3. 3: Satisfactory

16.5 points

Chart content describing the role of each emerging technology and how it correlates to information systems is incomplete or incorrect.

2. 2: Less Than Satisfactory

14.3 points

Chart content describing the role of each emerging and how it correlates to information systems is incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Chart content describing the role of each emerging technology and how it correlates to information systems is not included.

collapse Business Operations assessment

Business Operations

11 points

Criteria Description

Business Operations

5. 5: Excellent

11 points

Chart content describing how each technology could change business operations is thorough and includes substantial relevant supporting details.

4. 4: Good

9.35 points

Chart content describing how each technology could change business operations is complete and includes relevant supporting details.

3. 3: Satisfactory

8.25 points

Chart content describing how each technology could change business operations is included but lacks relevant supporting details.

2. 2: Less Than Satisfactory

7.15 points

Chart content describing how each technology could change business operations is incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Chart content describing how each technology could change business operations is not included.

collapse Competitive Advantage assessment

Competitive Advantage

11 points

Criteria Description

Competitive Advantage

5. 5: Excellent

11 points

Chart content describing how each technology could help a business organization gain competitive advantage is thorough and includes substantial relevant supporting details.

4. 4: Good

9.35 points

Chart content describing how each technology could help a business organization gain competitive advantage is complete and provides relevant supporting details.

3. 3: Satisfactory

8.25 points

Chart content describing how each technology could help a business organization gain competitive advantage is included but lacks relevant supporting details.

2. 2: Less Than Satisfactory

7.15 points

Chart content describing how each technology could help a business organization gain competitive advantage is incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Chart content describing how each technology could help a business organization gain competitive advantage is not included.

collapse Employee Work assessment

Employee Work

11 points

Criteria Description

Employee Work

5. 5: Excellent

11 points

Table content describing how each technology could change the way employees work is thorough and includes substantial relevant supporting details.

4. 4: Good

9.35 points

Table content describing how each technology could change the way employees work is complete and includes relevant supporting details.

3. 3: Satisfactory

8.25 points

Table content describing how each technology could change the way employees work is included but lacks relevant supporting details.

2. 2: Less Than Satisfactory

7.15 points

Table content describing how each technology could change the way employees work is incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Table content describing how each technology could change the way employees work is not included.

collapse Organizational Goals assessment

Organizational Goals

11 points

Criteria Description

Organizational Goals

5. 5: Excellent

11 points

Chart content describing how each technology could help an organization meet goals more quickly and efficiently is thorough and includes substantial relevant supporting details.

4. 4: Good

9.35 points

Chart content describing how each technology could help an organization meet goals more quickly and efficiently is complete and provides relevant supporting details.

3. 3: Satisfactory

8.25 points

Chart content describing how each technology could help an organization meet goals more quickly and efficiently is included but lacks relevant supporting details.

2. 2: Less Than Satisfactory

7.15 points

Chart content describing how each technology could help an organization meet goals more quickly and efficiently is incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Chart content describing how each technology could help an organization meet goals more quickly and efficiently is not included.

collapse Customer Interaction and Experience assessment

Customer Interaction and Experience

11 points

Criteria Description

Customer Interaction and Experience

5. 5: Excellent

11 points

Table content describing how each technology could change customer interaction or the customer experience is thorough and includes substantial relevant supporting details.

4. 4: Good

9.35 points

Table content describing how each technology could change customer interaction or the customer experience is complete and provides relevant supporting details.

3. 3: Satisfactory

8.25 points

Table content describing how each technology could change customer interaction or the customer experience is included but lacks relevant supporting details.

2. 2: Less Than Satisfactory

7.15 points

Table content describing how each technology could change customer interaction or the customer experience is incomplete or incorrect.

1. 1: Unsatisfactory

0 points

Table content describing how each technology could change customer interaction or the customer experience is not included.

collapse Documentation of Sources assessment

Documentation of Sources

5.5 points

Criteria Description

Documentation of Sources (citations, footnotes, references, bibliography, etc., as appropriate to assignment and style)

5. 5: Excellent

5.5 points

Sources are completely and correctly documented, as appropriate to assignment and style, and format is free of error.

4. 4: Good

4.68 points

Sources are documented, as appropriate to assignment and style, and format is mostly correct.

3. 3: Satisfactory

4.13 points

Sources are documented, as appropriate to assignment and style, although some formatting errors may be present.

2. 2: Less Than Satisfactory

3.58 points

Documentation of sources is inconsistent or incorrect, as appropriate to assignment and style, with numerous formatting errors.

1. 1: Unsatisfactory

0 points

Sources are not documented.

collapse Mechanics of Writing (includes spelling, punctuation, grammar, language use) assessment

Mechanics of Writing (includes spelling, punctuation, grammar, language use)

5.5 points

Criteria Description

Mechanics of Writing (includes spelling, punctuation, grammar, language use)

5. 5: Excellent

5.5 points

Writer is clearly in command of standard, written, academic English.

4. 4: Good

4.68 points

Prose is largely free of mechanical errors, although a few may be present. The writer uses a variety of effective sentence structures and figures of speech.

3. 3: Satisfactory

4.13 points

Some mechanical errors or typos are present, but they are not overly distracting to the reader. Correct and varied sentence structure and audience-appropriate language are employed.

2. 2: Less Than Satisfactory

3.58 points

Frequent and repetitive mechanical errors distract the reader. Inconsistencies in language choice (register) or word choice are present. Sentence structure is correct but not varied.

1. 1: Unsatisfactory

0 points

Surface errors are pervasive enough that they impede communication of meaning. Inappropriate word choice or sentence construction is used.

Electrical Engineering homework help

Sheet1

Benchmark – Applying Emerging Technology in Business
Techonlogy Blockchain Machine Learning Augmented Reality (AR)
Description of the role of the technology and how it correlates to information systems. Blockchain is a specific type of database that stores information in blocks that are then chained together. As new data comes in, it is entered into a fresh block. Once the block is filled with data, it is chained onto the previous block, connecting all data in chronological order. Mostly Blockchain is used as a ledger for transactions (BuiltIn, 2019). Machine learning is an application of artificial intelligence (AI) that provides systems the ability to automatically learn and improve from experience without being explicitly programmed. Machine learning focuses on the development of computer programs that can access data and use it to learn for themselves (EST, 2019). Augmented reality (AR) is an interactive technology of a real-world environment where the objects that reside in the real world, are enhanced by computer-generated algorithms to augment sound, video, graphics and other sensor based inputs on real world objects using the camera of your device (3Pillar Global, 2020).
Description of how the technology could change business operations. Blockchain technology can affect business operations for the better. Blockchain allows businesses to send and receive payments through a programmatic set of rules called “smart contracts” ( self-executing computer programs). As all actions related to a particular smart contract are transparent and recorded, this could also reduce the cost of tracking. Bringing transparency into the supply chain also helps in verifying things like the authenticity of parts and ethical sourcing (Carty, 2020). When using machine learning technology, it can help business operation by saving time on manual and repetitive tasks, accelerate mean time to resolution, and maintain greater control over IT infrastructure. By being powered by machine learning, companies today are using machine learning to target new audiences, communicate with consumers and find new customers (Fallon, 2020). Augmented reality will advance business’s operation by changing how industrial jobs are preformed. Technicians in the field will be able to receive live support from remote staff, who can indicate markings, point out issues, superimpose models over items like vehicle engines and the like, and more. It removes the grunt and the guesswork from manual work and streamlines processes (Fade, 2019).
Description of how the technology could change the way employees work. Blockchain affects the way employees work by allowing human resources (HR) to work ten times effectively. Without phone calls, emails or stacks of paper, the right talent can be authorized and brought in at each relevant step in the process. Background and employment-history checks can eliminate the chances of fraudulent applications. A smart contract creates enforceable and immutable rights and obligations for all participants.Making it easier for HR to automatically release payments from escrow once workers complete assigned tasks, which smooths income for workers and cash flow for companies. Compliance and regulations under Blockchain ensure employees have control over their own data (Masson, 2018). Machining technology (or AI’s) will affect the way employees work by improving work flow and decision making. Many employees lack is the ability to make efficient, productive decisions. AI’s will change how we work by providing more data-driven insights, which will lead to improved decision-making skills (Wellers, Elliott & Noga, 2017). Augmented reality will also assist with employees’ work/ training. Training programs, allowing employees to practice complex situations in a 3D environment. Which then allows companies to develop training that’s consistent for each employee and enables the employee to develop competence and confidence in their role (Fade, 2019).
Description of how the technology could change customer interaction or the customer experience. By using Blockchain, it ensures customers that they will have a positive and safe interaction with the company. Blockchain can step in between the customer and company, to verify that identity independently. The customer can trust it, and the company can trust it, because they both know that within the Blockchain identities cannot be changed.This will put the power over their identifying information back in the customer’s hands, and thereby improve the customer experience (Belleghem, 2018). Machine learning (AI), is continuously learning and improving from the data it analyzes, and is able to anticipate customer behavior. This allows brands to provide highly relevant content, increase sales opportunities, and improve the customer journey. Giving a personalized touch to the customer along with machines will result in improved customer satisfaction. (Clark, 2020). Augmented reality will affect the way customers interact, or shop with any company. By allowing for a more positive and visually pleasing shopping experience. Retailers are prioritizing customer experience and digital. With this blurring of the lines between digital and physical shopping, augmented reality will allow businesses to bridge the gap and introduce new and improved ways for customers to shop (Fade, 2019).
Description of how the technology could help business organizations gain competitive advantage. By using Blockchain technology, it give businesses a competitive advantage. Every single transaction is automated and seamless only because of smart contracts enabled by blockchain technology. Blockchain offers open banking, making it customizable for businesses to combine traditional banking and cryptocurrency services in a secure and user-friendly manner. By creating an automated, incorruptible and instantaneous contract, blockchain solutions will be able to eliminate costly intermediaries and the risks associated with drawn-out transactions (Medal, 2018). Through the use of machine learning technology, business can gain a competitive advantage both fro the company and for their customers. Machine learning can power through large amounts of data much faster than a human can on anything ranging from research and development reports, to customer satisfaction surveys. Meaning companies using machine learning get those data insights much faster and can apply them to their strategy before the competition. Machine learning can sort through data to provide an accurate and ever-changing picture of a company’s customers. All while measuring public opinion and how the brand is viewed on channels like social media. Lastly, machine learning can adapt to different databases and types of customers to provide the exact results people want. Which can make the entire customer experience much more convenient and enjoyable; making customers want to buy more, and businesses to profit from it ( Team, 2017). Through augment reality, business’s in the design and creative workplace can hold a higher advantage again their competitors. Industries in the design and creative spaces will likely be some of the markets most positively impacted by the introduction of augmented reality. By developing apps that give companies the ability to superimpose 3D models into physical spaces will allow them to deliver stronger sales and marketing material (Fade, 2019).
Description of how the technology could help the organization meet goals more quickly or efficiently. Blockchain technology assist businesses with meeting their goals by providing their employees with easy access to important company documents, so they can do their jobs faster. Blockchain eliminates the possibilities of fraud. Making things like audits quick and easy because of previous stored unaltered data to correctly asses and process information. Blockchain’s transparency also make event tracking easier, allowing for managers can quickly and easily track the origin of the problem to react faster to fix the problem. From cost reduction solutions to privacy enhancement to entirely new business models, blockchain holds tremendous potential for businesses (Navarro, 2019). As machine learning continues to develop, it will only enhance a business’s to achieving their overall goals more effectively and correctly. Machine learning has started revolutionizing the marketing sector as many companies have successfully implemented machine learning/ AI to increase and enhance customer satisfaction by over 10%. Healthcare wise, machine learning has allowed the use of wearable sensors/ devices that monitor everything from pulse rates, oxygen, sugar levels, etc. to generated a significant volume of data that enables doctors to assess their patients’ health in real-time. In the financial department, machine learning can help calibrate financial portfolios or assess risk for loans and insurance underwriting. It’s clear, based on a significant volume of data and evidence, that machine learning and AI are here to stay (Admin, 2020). As for augmented reality affecting business’s goals, it will increase the chances for their products to be sold, and increase their overall sales. AR is helping retailers to increase their brand positioning by enhancing the customer engagement. They allow their customers to interact with the product and making shopping more fun. AR applications are allowing customers scan products to get instant details before purchasing. This influence a customer’s buying decision and increase the chances of an actual purchase (Fade, 2019).
References Belleghem, S. (2018). How blockchain is changing customer experience through identity and trust | Steven Van Belleghem. Retrieved 13 January 2021, from https://www.stevenvanbelleghem.com/blog/how-blockchain-is-changing-customer-experience-through-identity-and-trust/#:~:text=By%20holding%20the%20keys%20to,Blockchain%20identities%20cannot%20be%20changed. Admin, Q. (2020). Why is Machine Learning Important and How will it Impact Business?. Retrieved 15 January 2021, from https://quantilus.com/why-is-machine-learning-important-and-how-will-it-impact-business/ 3Pillar Global. (2020). Augmented Reality – Introduction and its Real World Uses. Retrieved 15 January 2021, from https://www.3pillarglobal.com/insights/blog-posts/augmented-reality-introduction-and-its-real-world-uses/
BuiltIn. (2019). What Is Blockchain Technology? How Does It Work? | Built In. Retrieved 13 January 2021, from https://builtin.com/blockchain Clark, S. (2020). 4 Ways AI is Driving Better Customer Experience. Retrieved 14 January 2021, from https://www.cmswire.com/customer-experience/4-ways-that-ai-is-improving-the-customer-experience/ Fade, L. (2019). Council Post: Augmented Reality In Business: How AR May Change The Way We Work. Retrieved 15 January 2021, from https://www.forbes.com/sites/theyec/2019/02/06/augmented-reality-in-business-how-ar-may-change-the-way-we-work/?sh=1d01bb5e51e5
Carty, T. (2020). Is Blockchain Changing The Way Businesses Operate?. Retrieved 13 January 2021, from https://blog.etech7.com/is-blockchain-changing-the-way-businesses-operate Expert System Team (EST). (2019). What is Machine Learning? A definition – Expert System. Retrieved 14 January 2021, from https://www.expert.ai/blog/machine-learning-definition/#:~:text=Machine%20learning%20is%20an%20application,it%20to%20learn%20for%20themselves.
Masson, C. (2018). How will blockchain change employment?. Retrieved 13 January 2021, from https://www.peoplemanagement.co.uk/voices/comment/blockchain-change-employment#:~:text=Blockchain%20redefines%20how%20we%20interact,value%20is%20the%20coming%20revolution. Fallon, N. (2020). How Will Machine Learning Impact Your Business?. Retrieved 14 January 2021, from https://www.uschamber.com/co/run/technology/machine-learning-impact-on-business
Medal, A. (2018). These 6 Industries Are Using Blockchain to Gain a Competitive Advantage. Retrieved 14 January 2021, from https://www.entrepreneur.com/article/311164 Team, E. (2017). Gain a Competitive Advantage With Machine Learning – insideBIGDATA. Retrieved 14 January 2021, from https://insidebigdata.com/2017/05/27/gain-competitive-advantage-machine-learning/
Navarro, J. (2019). What can blockchain technology do for your business? | Hexacta. Retrieved 14 January 2021, from https://www.hexacta.com/what-can-blockchain-technology-do-for-your-business/#:~:text=The%20underlying%20business%20benefit%20of,by%20an%20encrypted%2C%20distributed%20database.&text=When%20business%20units%20have%20fast,knowing%20their%20data%20is%20valid Wellers, D., Elliott, T., & Noga, M. (2017). 8 Ways Machine Learning Is Improving Companies’ Work Processes. Retrieved 14 January 2021, from https://hbr.org/2017/05/8-ways-machine-learning-is-improving-companies-work-processes

Electrical Engineering homework help

1.For AlxGa1-xAs, find the composition with energy band gap 2 eV. Also find the effective mass at the Γ, X and the L valleys.

Use AlxGa1-xAs = 1.42 + 1.247x.

Effective mass at Γ valley is 0.067 + 0.083x; the X valley is 0.32 – 0.06x, and the L valley is 0.11 +0.03x, all in units of m*/m0

2. Consider a quantum box of GaAs of dimensions L x L x L. Assume infinite potential barriers and calculate the separation of the ground and the excited energy states as a function of L. If a separation of kBT is needed to observe the confinement effects, what is the maximum size of the L required to see these effects at 4K and at 300K.

3. A sample of GaAs has a free electron density of 1017 cm-3. Calculate the position of the Fermi level using the Boltzmann approximation and the Joyce Dixon approximation at 300K.

4. The absorption coefficients near the band edges of GaAs and Si are 104 cm-1 and 103 cm-1 respectively. What is the minimum thickness of a sample in each case that can absorb 90% of the incident light?

5. Consider a GaAs pn junction diode at T = 300 K with parameters Nd = 8 x 1016 cm-3, Na = 2 x 1015 cm-3, Dn = 207 cm2/s, Dp = 9.80 cm2/s, and τ0 = τp0 =τn0 = 5 x 10-8 s. (a) Calculate the ideal reverse-biased saturation current density. (b) Find the reverse-biased generation

current density if the diode is reverse biased at VR = 5 V. (c) Determine the ratio of J gen to Jsat.

6. Derive the density of states of 3D, 2D and 1D systems

7. Describe each of the following devices: solar cells, detectors, LEDs and lasers. Describe their similarities and differences.

8. Choose a specific type of a detector or a laser. You just need to pick one. Decide which material system you will use to design your device and why. Sketch a design of the device and describe its operation as well as the pros and cons of your device.

9. Describe a MODFET or a HEMT. Discuss why this is a superior system. Decide which material system you will use to design your device and why. Sketch a design of the device and describe its operation as well as the pros and cons of your device. What are the design issues you need to consider?

10. Pick a device based on quantum mechanical concepts where the wave nature of the electrons or their spins are important. Describe its fabrication and its operation. Discuss the pros and cons of such a device and its possible application. For this question you should look beyond what we covered in class and look at research papers or other books.

Electrical Engineering homework help

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS

ELECTRICAL ENGINEERING DEPARTMENT

EE 306 – Term 212

Course Design Project

(Due April 20, 2022 at 3:00PM)

Part I: Axial Fan Design

An axial flow fan is required to be installed for a large cooling tower. The fan needs to

deliver actual flow of 1.1 million cubic feet per minute (CFM) at actual static pressure of

0.477 +(0.your two-digit serial no., e.g., 0.01, 0.05, 0.12, 0.20, …etc) inch-H2O. To enhance

the operation of the fan, a velocity recovery (VR) stack is added.

You are required to design the fan and its driver (DC shunt motor) at the required operating

conditions.

Your design of the fan must consider the following:

 Temperature is set at 95o F

 Outlet-air temperature at sea level

 Total fan efficiency is in the range of 70%–85%

 Select the fan diameter based on your section number as follows:

Your Section Number Fan Diameter

3 20

6 22

7 24

8 26

9 28

10 30

 The VR stack will reduce the power of the fan so that the fan rated power equals to

the Air Horse-Power (AHP).

 The maximum feet per minute (FPM) is 18,000

 The fan is coupled with the motor via a gearbox with a ratio 1 to 4. Losses due to

gearbox could be neglected.

Your design for the fan should include the following calculations:

1. Velocity and total pressure

2. Selection of the diameter and number of blades for the fan

3. Air Horsepower (AHP) of the fan

4. Brake Horsepower (BHP) of the fan

5. Required pitch angle

Refer to the below document for guideline about axial fan design:

https://eurovent.eu/sites/default/files/field/file/PP%20-%202015-05-23%20-%20Attachment%20-

%20Hudson%20tip%20clearance%20example%20-%20page%2015%20-%20figure%206.pdf

Part II: DC Motor Design

Your design of the DC motor must consider the following:

 The efficiency of the motor must be between 85% to 90%.

 The brush losses in the machine is neglected

 The no load power should not exceed 7.5% of the output power.

 Speed regulation should not exceed 10%.

 The motor rated speed is available between 700 and 900 rpm.

 The supply voltage is 250V.

 The magnetization curve is linear and given as ϕ (Wb) =0.025If .

 The flux per pole should not exceed 25 mWb.

 The number of poles is up to 8 poles.

 The armature resistance is between (0.05 to 0.15) Ω.

Your design for the DC MOTOR should include the following calculations:

1. Output power, input power, copper losses, and rotational losses

2. Field current and field resistance

3. Armature current and motor input current

4. The machine constant Ka

5. Motor speed at no load and full load, and speed regulation

Electrical Engineering homework help

Principles of Electrical Engineering II
332:222 Spring 2022

Project #3
Please submit to Canvas by 11:59 PM Monday 4/2/22

Project format

For all the projects assigned in this course the following format is to be used

1. Each project is to have a title page, which will include the student name at the top of the
page as well as their student ID number. The project number will be centered on the title
page along with the submission date. For Project #3 also include “Design“ and either “A”, “B”,
or “C” as appropriate depending on the first letter of your last name. At the bottom of the title
page please write “Principles of Electrical Engineering II 332:222” and “Spring 2022”. The
page format should be based on 8.5″ x 11″ (American A sized) plain white paper for all the
pages in your report.

2. The title page will be followed by a brief introduction section, which will be one or two short
paragraphs long. After the introduction section the various project tasks will be answered.
Text must be typed. Schematic diagrams and graphs will be drafted and plotted using a com –
puter. Mathematical formulas may be neatly printed using either blue or black ink and then
scanned or typed using a word processor.

3. Class projects will be submitted to Canvas in PDF format. Please verify that your project
has been uploaded properly. Your project should be your own individual work.

Background

For this project you will be designing and simulating a three-way crossover network. These net –
works are commonly used in good quality stereo speaker systems. It turns out that it is difficult to get
a single cone speaker that can cover the entire audible range from 20 Hz to 20 kHz effectively. In a
three-way system three speakers are required. For deep bass a woofer for is used. This is the largest
speaker of the three and is suitable for reproducing sounds with a frequency of a couple of hundred
hertz or below. For the midrange frequencies a midrange speaker is used. It is typically able to repro-
duce sounds from a couple of hundred hertz to a few kilohertz. To reproduce the highest frequencies
a tweeter is used. It is the smallest speaker of the system and is able to reproduce sounds with fre-
quencies above a few kilohertz.

Each of these speakers works well to reproduce sounds within its designed frequency range. Op-
erating a speaker beyond that range of frequencies, however, will waste power and can potentially be
damaging. So it is important to make sure that the frequencies fed into each speaker (driver) are right
for them. In order to accomplish this task three passive filters are employed. For the tweeter a high-
pass filter is used. For the midrange frequencies a bandpass filter is employed. And for the deep
bass going to the woofer a low-pass filter is employed. When the outputs of these three filters are
combined a relatively flat all pass response will be observed. A stereo system has two identical copies
of the crossover network and speakers. One for the left channel and one for the right channel. For
our project, only one three way crossover system will be designed and simulated.

As the power output from a home stereo system can easily exceed 100W per channel a passive
filter network has to be employed. Active filters are not suitable for a speaker crossover network.

The Task

1. Using nodal analysis, find the transfer function H(s) for each filter subsection (high-pass, low-
pass, and bandpass) of the schematic in Fig. 1 in terms of L1, L2, L3, L4, C1, C2, C3, C4, and Rs-
peaker. For the purpose of this project assume that all three speakers have an impedance of
eight ohms (purely resistive).

2. Design your crossover network by finding the inductor and capacitor values that will provide
the desired response for your system. The desired system frequency response is as follows:

Given a 1 VRMS sinusoidal input into the combination of the three filters (as seen in Fig. 1) each
filter section will have a 1 VRMS (0 dB) output in the passband and a 0.5 VRMS (-6 dB) output at
the crossover frequency. In addition, the combined response of the three filter sections will
have a flat response within ±0.2 VRMS and the individual response of each of the three filter sec-
tions shall not exceed 1.2 VRMS. Note that some of the component values may need to be ad-
justed slightly in order to meet this design criteria. Also note that the crossover frequency is
not the same as the -3dB frequency.

The upper and lower crossover frequencies for your project will depend on the first letter of
your last name (as it appears on the official class roster) as specified in Table 1 below.

Note: Using crossover frequencies, for your project, other than the ones specified herein will
result in a 15% reduction in your overall grade for the project. Although a small deviation
(within ± 5%) in crossover frequency is allowed in order for you to meet the filter design criteria
above.

1st Letter of Your Last
Name

Lower Crossover Fre-
quency (Hz)

Upper Crossover Fre-
quency (Hz)

Design Type

A-H 100 2500 A

I-Q 250 5000 B

R-Z 400 6000 C
Table 1

3. Provide a Bode plot for each of your three filter section designs (high-pass, low-pass, and
bandpass) using the MATLAB ‘tf’ and ‘bode’ commands. Be sure to include a description under
each plot. Note that the MATLAB ‘bode’ command plots the frequency in radians per second
and not Hertz by default. The frequency axis should extend from 60 R/s to 600,000 R/s.

4. Using a SPICE circuit simulator (like LTSpice) simulate your three-way crossover system as
one combined circuit. The schematic diagram of the 3-way crossover is shown in Fig. 1.

Provide using SPICE:

• A bode magnitude and phase plot for the output of each filter section from 10 Hz to 100 kHz
(3 separate plots).

• One combined magnitude plot of the three filter sections in dB (add the 3 output voltages to-
gether) versus frequency from 10 Hz to 100 kHz.

• One combined magnitude plot of the three filter sections in linear volts (add the 3 output volt-
ages together) versus frequency from 10 Hz to 100 kHz.

• Be sure include a description below each of these plots.

• Plot these graphs on a white background.

Note: Please completely read the Project Tips section before starting your design. Trust me,
this will save you a lot of time and make the project much easier.

Fig. 1
Format

Each report is to be your individual work and is to be typed using a word processor. All of the plots
will be performed using a computer with the specified software. The derivation of H(s) for the system
and the design equations may be handwritten and scanned, if and only if, they are neatly printed, large
enough to be clearly readable, and done in blue or black. Use only a US standard 8-1/2” X 11” paper
size when setting up the page size for your report. Reports will be submitted to Canvas in pdf format
only.

The first page of the report will be a title page. It will have the format specified in the first page of
this project description.

The rest of the report will be broken up into the following sections (start each section on a new
page):

A) Derivation of H(s) for all three filters in the crossover system.
B) Filter design. Give a complete and detailed description of how you designed the three pas-

sive filters that make up your crossover network. I am looking for equations more than words
here.

C) MATLAB bode plots. Be sure to label all of your plots and make them big enough to be easily
readable.

D) SPICE schematic (the complete crossover with the three filter sections) with component values
and the plots (put the schematic first). Be sure to label all of your plots and make them big
enough to be easily readable. Make sure these plots have a white background.

Principle of Electrical Engineering II Project #3 Tips
Please read this before beginning the project or you will be really lost!

First, You want to get the transfer function for all 3 filters (LP, HP, & BP) individually. You do
this using nodal analysis. Yes, it is also possible to use the voltage divider rule. But I don’t
recommend it for the bandpass filter connected to the midrange speaker. It works in theory,
but will require a massive amount of algebra to get the solution. Don’t plug in any numbers in
yet. Solve for the H(s)’s in terms of L1, C1, s, Vin, Vout, etc. The LP and HP filters are easy –
there is only one node (not counting the ground node). Be sure to get these 2 transfer func-
tions in standard form. That is the denominator will be of the form s2+2αs+ ω0

2 .

The BP filter has 2 nodes (other than the ground node) to deal with. So you will get a set of
two equations. There will be two unknown voltages to solve for one of which will be V out.

Now, while it is possible to do this by hand, that is a long process. The easiest way is to use
MATLAB to solve the system of two equations for you or you can use a TI-89 calculator to do
the same thing. Personally I think MATLAB is the easiest way to go. Before entering the ma-
trix equation of the nodal system enter this command.

>> syms s L2 L3 C2 C3 Vin R

This will allow MATLAB to work with symbols instead of numbers. You are solving the nodal
system of equations this way:

A⃗ x⃗ = B⃗ so to find x⃗ enter this into MATLAB A⃗−1⋅B⃗ . The resulting vector x⃗ = [ VaVout]
. Vout is the solution that you are looking for. Now MATLAB will give you the solution but it
probably won’t be in the exact form that you need. So for both the numerator and denomina –
tor group the like powers of s. This will allow you to easily do a Bode plot using MATLAB.

The next step is to design the lowpass and highpass filter sections. An important point to re –
alize is that the crossover frequencies are not the same thing as the cutoff frequencies.
Things are a little different with this project than the material that we covered in class. The
idea is to split an incoming signal (say music) into 3 frequency ranges so each speaker can
be fed with a frequency range that it can reproduce best. When it comes to a point where two
frequency ranges overlap (the crossover frequency) you want the total of the two separated
signals to add up to the original signal at that point. The amplitude at the crossover frequen –
cies is 0.5V but at the cutoff frequencies the amplitude is 0.7071V. If you add two signals to –
gether (where the two filter responses intersect) at that amplitude you get 1.414 which is
higher than the 1 volt the signal level should be and the sound reproduced by the speakers
would be louder at that point (actually, this is a simplification – but it explains the concept).
So, to maintain an overall flat response (the total of all 3 of the separated signals adding up to
1V over the entire frequency spectrum) you need to define a “crossover point” at 1/2 of the in –
coming signal level or 0.5V.

The crossover frequencies are ω0 in the transfer functions for the LP and HP filter sections.
Be sure to multiply the frequencies specified in the project description, which is specified in
Hz, by 2π in order to convert them to radians/second.

Once you have H(s) for the lowpass and highPass filter sections look at the terms in the de-

nominator (when it is in standard form). The constant term is ω0
2 =

1
LC

. The ‘s’ term is re-

lated to the damping factor which corresponds to 2α .

You are going to work with the critically damped case. Remember the formula
−α±√α2−ω02 ? You will have a double real root when ω02 = α2 . Now ω0 is the cross-

over frequency in radians per second and R=8 Ohms. Knowing α , ω0 , and R=8 ohms
will set the values of L and C.

For the bandpass filter design you can multiply the HP and LP transfer functions to get an
APPROXIMATE transfer function for design purposes. You don’t have to work with this di –
rectly (use the true bandpass transfer function, that you determined as described above, to do
the MATLAB plots). But you should realize from this that the bandpass filter can be de-
signed as a cascaded highpass filter followed by a lowpass filter. This approximation is
possible because the two crossover frequencies are widely separated.

As to finding the L’s and C’s for the bandpass filter you don’t have to calculate everything
from scratch. The trick is the highpass section of the bandpass filter will have a crossover fre –
quency that is the same as the lower crossover frequency that is used for designing the low –
pass filter used with the woofer. The lowpass section of the bandpass filter will have a cross –
over frequency that is the same as the higher crossover frequency used to design the high –
pass filter used with the tweeter.

If you go through the calculations looking at the HP and LP sections individually you will find
that the L & C values for the bandpass filter are the sames as the L & C values for the low –
pass and highpass filters. You just have to get the correct values in the right place.

Once you have all of the needed L and C values use MATLAB (or Octave) to plot the trans –
fer functions for the 3 filter sections. Use these two commands:

>> h=tf([ Put the transfer function coefficients here! ])
>> bode(h)

The next step is to simulate the system using one of the SPICE circuit simulators. I used LT –
Spice but which one you use is up to you.

The schematic should look just like the one in the project description (all 3 filters sections
combined). Place your component values in the schematic and then select AC analysis. Set
the upper and lower frequency limits for the simulation as recommended and use 500 points
or so per decade for a smooth plot.

Run the simulation. Then, place the voltage probe at the non-grounded side of the resistor
(speaker) in each filter section. For the first plot I recommend leaving the magnitude in dB so

you can easily compare the results to your MATLAB plots. Note that by default MATLAB does
the Bode plots in angular frequency (Rad/Sec) and Spice does the plots in Hz. You are free
to set the option for MATLAB to do the Bode plots in Hz if you like but Rad/Sec is also OK.

For the combined response plot I recommend setting the vertical scale to linear volts. While
dB is still a valid choice the dB values for the design requirements work out to be fairly
strange numbers so working directly in volts is more convenient.

Please display your plots on a white background and make sure the trace lines are thick
enough so they can be easily seen on your plots.

The 3 filters individually only have an (approximate) 0.5 V magnitude at the two crossover
frequencies. I say approximate because the trick of assuming the bandpass filter is a cas-
caded highpass/lowpass filter combination is not exact. But you should get very close to the –
6 dB that you are designing for. If you did things correctly you should be very close. If your
bandpass crossover frequencies are a little off you can ‘tweak’ one or two of your L and/or C
values to get it within the design specifications.

Now, an ideal filter response, based on the straight line approximations that we used for the
Bode plots, is flat in the passband and drops off linearly (on a logarithmic scale) once you
pass the break frequency. So you could, in theory, by adding the 3 filtered outputs, get a con-
stant 1V amplitude across the full frequency range. But real filters do not have a response
that is perfectly flat in the passband and linear in the stopband. The real response of filters
are curved lines so if you add two or more filter responses together the total won’t be a per-
fectly flat (constant) 1V across the full frequency range. With careful design you can get a
more or less 1V total but it will vary a bit because the real world design is based on approxi –
mations and assumptions. That is where the +/- 0.2 V comes from. Over the entire frequency
range of interest the sum of all 3 of the filter outputs should not go below 0.8 V or above 1.2 V.
The COMBINED (added absolute values) magnitude response of all 3 filters should not devi –
ate more than +/- 0.2V from that 1V value over the entire frequency range. It turns out with
careful design you will probably achieve this on your first try. To combine the 3 filter outputs
using LTSpice you want to add a trace to the plot. There will be a location at the bottom of the
window that pops up for you to add a formula. Since you are adding magnitudes your formula
should look like this: abs(1st node voltage) + abs(2nd node voltage) + abs(3rd node voltage)

I know this is the most challenging of the three projects that I am assigning this semester.
But it is a real-world design problem and it is appropriate for a course of this level. I am giving
everyone this document as a guide to greatly reduce the work involved. Once you under –
stand all the tricks involved in this design you should be able to work through it in a half a day
or so. Reading this project description, doing the design work and simulations, and the doing
the project write-up should only take about one day all combined. Like most things in my
class I want it to be fun and not painful.

Good Luck!

– John McGarvey

Electrical Engineering homework help

See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/339750821

A Closed-Form Solution for Temperature Profiles in Selective Laser Melting of

Metal Additive Manufacturing

Conference Paper · March 2020

CITATIONS

0
READS

204

2 authors, including:

Some of the authors of this publication are also working on these related projects:

Selective laser melting View project

Analytical Modeling of Machining and Additive Manufacturing View project

Jinqiang Ning

Georgia Institute of Technology

50 PUBLICATIONS   772 CITATIONS   

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All content following this page was uploaded by Jinqiang Ning on 06 March 2020.

The user has requested enhancement of the downloaded file.

A Closed-Form Solution for Temperature Profiles in Selective Laser
Melting of Metal Additive Manufacturing

Steven Y. Liang1,a, Jinqiang Ning1,b and Elham Mirkoohi1
1George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, 801 Ferst

Drive, Atlanta, GA 30332, USA.
Correspondence: asteven.liang@me.gatech.edu, bjinqiangning@gatech.edu

Keywords: Selective Laser Melting; Closed-form solution; Temperature prediction; Selective laser
melting; Part boundary; Latent heat; High computational efficiency.

Abstract. This paper presents a closed-form solution for the temperature prediction in selective laser
melting (SLM). This solution is developed for the three-dimensional temperature prediction with
consideration of heat input from a moving laser heat source, and heat loss from convection and
radiation on the part top boundary. The consideration of heat transfer boundary condition and latent
heat in the closed-form solution leads to an improvement on the understanding of thermal
development and prediction accuracy in SLM, and thus the usefulness of the analytical model in the
temperature prediction in real applications. A moving point heat source solution is used to calculate
the temperature rise due to the heat input. A heat sink solution is used to calculate the temperature
drop due to heat loss from convection and radiation on the part boundary. The heat sink solution is
modified from a heat source solution with equivalent power due to heat loss from convection and
radiation, and zero-moving velocity. The temperature solution is then constructed from the
superposition of the linear heat source solution and linear heat sink solution. Latent heat is considered
using a heat integration method. Ti-6Al-4V is chosen to test the presented model with the assumption
of isotropic and homogeneous material. The predicted molten pool dimensions are compared to the
documented values from the finite element method and experiments in the literature. The presented
model has improved prediction accuracy and significantly higher computational efficiency compared
to the finite element model.

Introduction
Selective laser melting (SLM) is a widely used metal additive manufacturing (AM) process, in

which high-density laser powder is used to fully melt and fuse metal powders to build parts in a
layer-by-layer manner. Defects such as distortion, crack and balling effect are frequently observed
due to the large thermal gradient caused by the repeatedly rapid heat and solidification in SLM [1-3].

Experimental temperature measurements are difficult and inconvenient due to the restricted
accessibility under extremely high temperatures [4-6]. Infrared (IR) camera can measure the
temperature profile only on the exposed surfaces [7]. The embedded thermocouple can measure the
temperature history only in the far field, typically inside the substrate [8]. The metallographic
technique is also employed for post-process measurement of molten pool geometry based on the
solidification microstructure, which requires extensive experimental work [9]. Therefore, numerical
models and analytical models are developed for convenient temperature prediction in SLM.

Numerical models have been developed based on the finite element method (FEM), in which the
temperature, residual stress, and distortion were investigated [9-12]. Although the numerical models
have made considerable progress in the prediction of the SLM process, the expensive computational
cost is still the major drawback.

Analytical models have demonstrated their high computational efficiency in the prediction of
manufacturing processes [13-14]. To overcome the aforementioned drawbacks, analytical models
were developed for temperature prediction in the AM processes using closed-form solutions [15].
Temperature models were developed using point moving heat source, line moving heat source,
semi-ellipsoidal moving heat source, and uniform moving heat source [16,17]. All solutions were
developed for a 3D semi-infinite body without considering heat loss at the part boundary from

Materials Science Forum Submitted: 2019-06-12
ISSN: 1662-9752, Vol. 982, pp 98-105 Accepted: 2019-06-27
© 2020 Trans Tech Publications Ltd, Switzerland Online: 2020-03-20

All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans
Tech Publications Ltd, www.scientific.net. (#537514887, Morris M. Bryan, China-06/03/20,22:53:15)

convection and radiation. The temperature distribution in the direct metal deposition was predicted
using the moving point heat source solution with the assumption of the homogeneous and isotropic
solid workpiece. Good agreements were observed based upon validation to experimental results [18].
The temperature model was further developed with consideration of build layers, latent heat and
temperature-sensitive material properties [19]. An in-process temperature model was developed to
predict molten pool evolution with consideration of laser absorption, latent heat, scanning strategy
and powder packing [20]. However, the heat loss due to the convection and radiation at part boundary
has not been considered in the developed models. FEM must be used with the analytical model to
properly impose the boundary conditions [21], which resulted in an unoptimized computational
efficiency. The neglection of the heat transfer boundary condition significantly reduced the
usefulness of other developed analytical models in real applications because of the temperature
overestimation. The neglection of the latent heat also leads to the overestimation because of the
neglection of energy required for phase transformation.

This work presents an analytical model for the temperature prediction in SLM with consideration
of heat loss at the top boundary due to convection and radiation. The heat input from laser power is
calculated using the moving point heat source solution. The heat source solution is modified for the
consideration of the heat loss due to the convection and radiation with equivalent power loss and zero
velocity. The final solution is constructed from the superposition of the heat source solution and heat
sink solutions. The presented model is employed to predict the temperature distribution in the SLM of
Ti-6Al-4V under various process conditions. Molten pool dimensions are determined from the
predicted temperatures by comparing them to the material melting temperature as illustrated in Fig. 1.
The molten pool dimensions are validated to the experimental values in the literature, which were
measured based on the solidification microstructure. In addition, the molten pool dimensions from the
presented model are compared to that adopted from the FEM model regarding prediction accuracy
and computational efficiency.

Fig. 1. Schematic view of molten pool geometry. P, W, L, D denote the moving laser power, molten
pool width, molten pool length, and molten pool depth respectively. The red arrow denotes laser heat

source input. The blue arrows denote heat loss on the top surface due to convection and radiation

Material and Methodology
In this work, a closed-form solution is developed for the temperature prediction in SLM with

consideration of convection and radiation at the part boundary. Temperature increase due to the laser
power input is calculated using the moving point heat source solution as the following.

𝜃𝜃𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) =
𝑃𝑃𝑃𝑃

4𝜋𝜋𝜋𝜋𝜋𝜋(𝑇𝑇𝑚𝑚 − 𝑇𝑇0)
exp �

−𝑉𝑉(𝜋𝜋 + 𝑥𝑥)
2𝜅𝜅


(1)

where 𝑃𝑃 is laser power, 𝑃𝑃 is laser absorption, 𝑉𝑉 is scanning speed, 𝜋𝜋 is conductivity, 𝜅𝜅 is diffusivity
(𝜅𝜅 = 𝑘𝑘

𝜌𝜌𝑠𝑠
, 𝜌𝜌 is materials density, c is specific heat), 𝜋𝜋 is the distance from the laser heat source location

Materials Science Forum Vol. 982 99

(𝜋𝜋 = �𝑥𝑥2 + 𝑦𝑦2 + 𝑧𝑧2, x, y, z are the distance from the laser heat source along three mutually
perpendicular axes), 𝑇𝑇0 is the room temperature, and 𝑇𝑇𝑚𝑚 is the material melting temperature.

Temperature decrease due to the heat loss from convection and radiation is calculated using the
heat sink solution, which is derived by modifying the heat source solution with equivalent power loss
and zero moving speed. The non-moving part boundary is mathematically discretized into many
sections, and each section is now named heat sink. The equivalent power loss due to convection and
radiation at each heat sink are expressed as the following.
𝑄𝑄𝑠𝑠𝑠𝑠𝑐𝑐𝑐𝑐 = 𝐴𝐴ℎ(𝑇𝑇 − 𝑇𝑇0)

(2)
𝑄𝑄𝑠𝑠𝑟𝑟𝑟𝑟 = Aεσ(𝑇𝑇4 − 𝑇𝑇04)

(3)
where ℎ is heat convection coefficient, ε is emissivity, σ is Stefan-Boltzmann constant, A is the area
of each heat sink, T is the temperature of each heat sink that can be estimated using the point moving
heat source solution.

The heat sink solution at the part boundary is expressed as the following.

𝜃𝜃𝑠𝑠𝑠𝑠𝑐𝑐𝑘𝑘(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = �
𝐴𝐴𝑠𝑠

4𝜋𝜋𝜅𝜅𝜋𝜋𝑠𝑠(𝑇𝑇𝑚𝑚 − 𝑇𝑇0)
[ℎ(𝑇𝑇𝑠𝑠 − 𝑇𝑇0) + εσ(𝑇𝑇𝑠𝑠

4 − 𝑇𝑇04) ]
𝑐𝑐

𝑠𝑠=1

(4)
where 𝑖𝑖 denotes the index of the heat sink, 𝑛𝑛 denotes the total number of heat sinks, 𝜋𝜋𝑠𝑠 is the distance
from the heat sink location.

Finally, the temperature solution is constructed from the superposition of heat source solution and
heat sink solutions as expressed in the following.
𝜃𝜃(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝜃𝜃𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 − 𝜃𝜃𝑠𝑠𝑠𝑠𝑐𝑐𝑘𝑘 =

𝑃𝑃𝑃𝑃

4𝜋𝜋𝜋𝜋𝜋𝜋(𝑇𝑇𝑚𝑚 − 𝑇𝑇0)
exp �

−𝑉𝑉(𝜋𝜋 + 𝑥𝑥)
2𝜅𝜅

� − �
𝐴𝐴𝑠𝑠

4𝜋𝜋𝜅𝜅𝜋𝜋𝑠𝑠(𝑇𝑇𝑚𝑚 − 𝑇𝑇0)
[ℎ(𝑇𝑇𝑠𝑠 − 𝑇𝑇0) + εσ(𝑇𝑇𝑠𝑠

4 − 𝑇𝑇04) ]
𝑐𝑐

𝑠𝑠=1

(5)
where 𝜃𝜃 is the dimensionless temperature that can be expressed as

𝜃𝜃 =
𝑇𝑇 − 𝑇𝑇0
𝑇𝑇𝑚𝑚 − 𝑇𝑇0

(6)
The latent heat is considered in the presented model using an integration method as expressed in

the following.


𝑇𝑇 = 𝑇𝑇𝑆𝑆 (𝑇𝑇𝑆𝑆 < 𝑇𝑇 < 𝑇𝑇𝐿𝐿)

𝑇𝑇 = 𝑇𝑇 −
𝐿𝐿𝑓𝑓
𝑐𝑐

(𝑇𝑇 > 𝑇𝑇𝐿𝐿)

(7)
where 𝑇𝑇𝑆𝑆 is solidus temperature, 𝑇𝑇𝐿𝐿 is liquidus temperature, 𝐿𝐿𝑓𝑓 is the latent heat, 𝑐𝑐 is specific heat.

Results and Discussion
To investigate the prediction accuracy and computational efficiency of the presented model, the

temperature distribution in the SLM of Ti-6Al-4V was predicted under various process conditions as
given in Table 1. The build body was assumed to be isotropic and homogeneous with boundary
condition imposed on the top surface. The materials properties of Ti-6Al-4V and heat transfer
coefficients are given in Table 2.

100 Advanced Materials and Processing Technologies II

Table 1. Process conditions in the selective laser melting of Ti-6Al-4V [9]
Test 𝑃𝑃 [𝑊𝑊] 𝑉𝑉[mm/s]

1 20 200
2 40 200
3 60 200
4 80 200

Table 2. Material properties of Ti-6Al-4V [9]

Name Value Unit

Density (𝜌𝜌) 4428 [Kg/m3]

Heat capacity (𝐶𝐶𝑝𝑝) 580 [J/kg-K]

Bulk thermal conductivity (𝜋𝜋𝑡𝑡) 7.2 [W/m-K]

Melting temperature (𝑇𝑇𝑚𝑚) 1655 [oC]

Room temperature (𝑇𝑇0) 20 [oC]

Solidus temperature (𝑇𝑇𝑠𝑠) 1605 [oC]

Liquidus temperature (𝑇𝑇𝑙𝑙) 1655 [oC]

Absorption (𝑃𝑃) 0.77 [1]

Latent heat (𝐻𝐻𝑓𝑓) 365000 [J/Kg]

Heat Convection coefficient (ℎ) 24 [W/m2-K]

Stefan–Boltzmann constant (𝜎𝜎) 5.67 10-8 [W/m2-K4]

Radiation emissivity (𝜀𝜀) 0.9 [1]

The temperatures distribution was predicted near laser heat source location under various process
conditions as illustrated in Fig. 2, in which the temperature profiles were plotted with a top view
while laser scanned along x-direction at x = 0.4 mm, y = 0.25 mm. The larger the laser power, the
larger the heat affected zone, and vice versa. This observation is consistent with the instinctive trend.

Materials Science Forum Vol. 982 101

Fig. 2. Top view temperature distribution in SLM of Ti-6Al-4V alloy under (a) test 1, (b) test 2, (c)
test 3, (d) test 4 process conditions

The temperature distribution was also plotted along the molten width direction and molten pool
depth direction under the test 1 process condition as illustrated in Fig. 3. The maximum temperature
in the SLM under the test 1 process condition was about 4000 oC. The maximum temperature was
higher than the material melting temperature due to the highly concentrated energy from the point
heat source, which indicated the existence of material evaporation. The material evaporation was
confirmed from the experimental observation in the literature, in which a laser with a spot radius of
26 μm was employed [9]. The smaller the laser spot radius, the higher the concentrated energy.
Symmetric temperature distributions were observed along the width direction (y-direction) as shown
in Fig. 3a. Small regions of constant temperatures were observed due to the consideration of latent
heat, in which the phase transformation took place instead of temperature rise with continuous heat
input.

Fig. 3. Temperature distribution (a) along width direction (y-direction) and (b) depth direction
(z-direction)

The molten pool dimensions are determined from the predicted temperatures by comparing to the
material melting temperature. The obtained molten pool dimensions are compared to FEM values and
to the experimental values in the literature [9]. Experimental measurements of the molten pool depth
and width were conducted based on the solidification microstructure. The molten pool volume was
calculated as the following.

𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 =
𝜋𝜋𝜋𝜋𝑊𝑊𝐿𝐿

6

(8)

102 Advanced Materials and Processing Technologies II

where 𝜋𝜋, 𝑊𝑊, 𝐿𝐿 are the molten pool depth, molten pool width and molten pool length
respectively.

The molten pool dimensions of molten pool width, depth, length, and volume under four different
process conditions were shown in Fig. 4. The larger the laser power, the larger the molten pool
dimensions, and vice versa. The predicted molten pool depth and length using the presented model
demonstrated an improved prediction accuracy, compared to the available FEM results in the
literature [9]. The prediction using the presented model was implemented using a MATLAB program
on a personal computer running at 2.8 GHz. The average computational time was recorded as 12 s.
For comparison, FEM usually needs hours of time depending on the part size and mesh resolution for
a comparable prediction accuracy [22,23].

In addition, the balling effect was investigated based on the molten pool length to width ratio. The
molten pool length to width ratio from the prediction was smaller than the critical value 𝜋𝜋 [24],
which indicated that no concentrated balling effect existed. This finding confirmed the experimental
observation in the literature [9].

Fig. 4. Comparison between experimental measurements (black color), documented results from the
finite element model (red color) and predicted results using the presented model (blue color). Plots

(a-d) represents the molten pool width, depth, length, and volume respectively under various process
conditions

Conclusion
This paper presents a closed-form solution for the temperature prediction in SLM with

consideration of heat loss at the part top boundary, and latent heat. The lack of consideration of the
heat transfer boundary condition in previously developed analytical models reduced their prediction
accuracy. This temperature solution is constructed from the superposition of the moving point heat
source solution and heat sink solutions. The latter is derived by modifying the former with equivalent
power due to heat loss from convection and radiation at the part boundary and zero moving velocity.
Ti-6Al-4V was chosen to investigate the prediction accuracy and computational efficiency of the
presented temperature model under various process conditions. Molten pool dimensions obtained

Materials Science Forum Vol. 982 103

from the predicted temperatures were compared to the FEM results and experimental measurements
in the literature. Improved prediction accuracy and considerably higher computational efficiency
were observed with the presented model, compared to the documented FEM results. In the future, the
developed closed-form solution can be used to impose boundary condition on the lateral boundary
and geometrical complex boundary.

References
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distortion during laser cladding of Inconel® 625. Journal of Materials Processing Technology,
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[2] Gong, H., Rafi, K., Gu, H., Starr, T., & Stucker, B. (2014). Analysis of defect generation in Ti–
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[3] Li, R., Liu, J., Shi, Y., Wang, L., & Jiang, W. (2012). Balling behavior of stainless steel and
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[4] Ning, J., & Liang, S. Y. (2018). Prediction of Temperature Distribution in Orthogonal
Machining Based on the Mechanics of the Cutting Process Using a Constitutive Model. Journal
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[5] Ning, J., & Liang, S. Y. (2018). Evaluation of an Analytical Model in the Prediction of
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[6] Ning, J., & Liang, S. Y. (2019). Predictive modeling of machining temperatures with
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[7] Peyre, P., Aubry, P., Fabbro, R., Neveu, R., & Longuet, A. (2008). Analytical and numerical
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41(2), 025403. doi:10.1088/0022-3727/41/2/025403

[8] Everton, S. K., Hirsch, M., Stravroulakis, P., Leach, R. K., & Clare, A. T. (2016). Review of
in-situ process monitoring and in-situ metrology for metal additive manufacturing. Materials &
Design, 95, 431-445. https://doi.org/10.1016/j.matdes.2016.01.099

[9] Fu, C. H., & Guo, Y. B. (2014). Three-dimensional temperature gradient mechanism in
selective laser melting of Ti-6Al-4V. Journal of Manufacturing Science and Engineering,
136(6), 061004. doi: 10.1115/1.4028539

[10] Roberts, I. A., Wang, C. J., Esterlein, R., Stanford, M., & Mynors, D. J. (2009). A
three-dimensional finite element analysis of the temperature field during laser melting of metal
powders in additive layer manufacturing. International Journal of Machine Tools and
Manufacture, 49(12-13), 916-923. https://doi.org/10.1016/j.ijmachtools.2009.07.004

[11] Li, C., Liu, J. F., & Guo, Y. B. (2016). Prediction of residual stress and part distortion in
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[12] Afazov, S., Denmark, W. A., Toralles, B. L., Holloway, A., & Yaghi, A. (2017). Distortion
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104 Advanced Materials and Processing Technologies II

[13] Ning, J., & Liang, S. Y. (2019). A comparative study of analytical thermal models to predict the
orthogonal cutting temperature of AISI 1045 steel, The International Journal of Advanced
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[14] Ning, J., Nguyen, V., & Liang, S. Y. (2018). Analytical modeling of machining forces of
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[15] Van Elsen, M., Baelmans, M., Mercelis, P., & Kruth, J. P. (2007). Solutions for modelling
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[16] Carslaw, H. S., & Jaeger, J. C. (1959). Conduction of heat in solids: Oxford Science
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[17] Rosenthal, D. (1946). The theory of moving sources of heat and its application of metal
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[18] de La Batut, B., Fergani, O., Brotan, V., Bambach, M., & El Mansouri, M. (2017). Analytical
and numerical temperature prediction in direct metal deposition of Ti6Al4V. Journal of
Manufacturing and Materials Processing, 1(1), 3. https://doi.org/10.3390/jmmp1010003

[19] Mirkoohi, E., Ning, J., Bocchini, P., Fergani, O., Chiang, K. N., & Liang, S. (2018). Thermal
modeling of temperature distribution in metal additive manufacturing considering effects of
build layers, latent heat, and temperature-sensitivity of material properties. Journal of
Manufacturing and Materials Processing, 2(3), 63. https://doi.org/10.3390/jmmp2030063

[20] Ning, J., Sievers, D. E., Garmestani, H., & Liang, S. Y. (2019). Analytical Modeling of
In-Process Temperature in Powder Bed Additive Manufacturing Considering Laser Power
Absorption, Latent Heat, Scanning Strategy, and Powder Packing. Materials, 12(5), 808.
https://doi.org/10.3390/ma12050808

[21] Yang, Y., Knol, M. F., van Keulen, F., & Ayas, C. (2018). A semi-analytical thermal modelling
approach for selective laser melting. Additive Manufacturing, 21, 284-297.
https://doi.org/10.1016/j.addma.2018.03.002

[22] Schoinochoritis, B., Chantzis, D., & Salonitis, K. (2017). Simulation of metallic powder bed
additive manufacturing processes with the finite element method: A critical review.
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Manufacture, 231(1), 96-117. https://doi.org/10.1177/0954405414567522

[23] Roberts, I. A., Wang, C. J., Esterlein, R., Stanford, M., & Mynors, D. J. (2009). A
three-dimensional finite element analysis of the temperature field during laser melting of metal
powders in additive layer manufacturing. International Journal of Machine Tools and
Manufacture, 49(12-13), 916-923. https://doi.org/10.1016/j.ijmachtools.2009.07.004

[24] Kruth, J. P., Levy, G., Klocke, F., & Childs, T. H. C. (2007). Consolidation phenomena in laser
and powder-bed based layered manufacturing. CIRP Annals, 56(2), 730-759.
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Materials Science Forum Vol. 982 105

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Electrical Engineering homework help

• Type your report in word or pdf format: at least 6 pages excluding the cover page (title, name, affiliation, etc.)

• Prepare the report using ASME conference paper template (can be downloaded from ASME website)

• The report should include the followings: – Title, abstract, and your name – Literature review (It is suggested that least 10 related papers are reviewed to describe the state-of-the-art on the subject). – Summary of the work in the reference paper you selected, such as PDFs, BSc, ICs, solution method, solutions, etc. – Your proposed work and its objectives.

• Describe what’s new or the difference in your work as compared to the existing papers (they can be different assumptions, BC/IC conditions, physics, or solution methods).

• Use 1-2 schematic drawings to illustrate the physical problem if variations are made. – Results and discussions

• Use a tool, such as Excel or any other software, to plot the typical solution from the reference paper your selected.

• Investigate the effects of key parameters on the solutions using existing solutions • Compare your new solution with existing ones.

• Discuss the pros and cons of different solutions in the context of heat transfer analysis. – Conclusions – List of References Cited.

Electrical Engineering homework help

ESE 232 – Introduction to Electronic Circuits (Spring 2022)

Problem 1 (15 points): (Solving time ~10min)

A. Solve the circuit above and find 𝑣𝑥 and 𝑖𝑥. (5 points)

B. Is the 1mA current source, dissipating or generating power? What is power dissipated/generated by the 1mA current source? (5 points)

C. Is the 1V voltage source, dissipating or generating power? What is the power dissipated/generated by the 1V voltage source? (5 points)

Problem 2 (15 points): (Solving time ~10min)

You are required to design a surge protection circuit as shown below using semiconductor diodes with VD,ON = 1V and current handling of 10mA.

A. Draw the schematic of the surge protection circuit that ensures the output voltage (Vout) always lie between -1V and +2V, irrespective of the input voltage (Vin). (Note: The circuit “N” should only have diodes. It has no DC voltage sources.) (10 points)

B. For -5V< Vin < +5V, choose the minimum value of Rs such that the current through the diodes does not exceed their current handling. (5 points)

Problem 3 (15 points): (Solving time ~10min)

Above schematic shows a capacitor-coupled attenuator circuit. Assume C1 and C2 are very large and does not effect the small signal gain at AC frequencies. Both diodes D1 and D2 are semiconductor diodes with following properties.

Diode D1: Saturation current, Is = 2uA, non-ideality factor, 𝜂 = 1.5. (Assume Vt = 25mV)

Diode D2: Saturation current, Is = 1uA, non-ideality factor, 𝜂 = 1.5. (Assume Vt = 25mV) A. Assuming Io is positive, draw the small signal equivalent circuit and express the small signal resistances of the diodes D1 (rd1) and diode D2 (rd2) as a function of current Io. (5 points)

B. Plot the small signal gain (𝑣𝑜𝑢𝑡/𝑣𝑖𝑛) as a function of Io. Assume Io varying between 0 and 2mA. (4 points)

C. What is the small signal gain when Io = 0.5mA, 1mA, and 1.5mA. (6 points)

Problem 4 (15 points): (Solving time ~10min)

Find Io, V1, V2, V3, and V4. (3 points each)

Note: In the final answer, all transistors are in saturation region.

Problem 5 (15 points): (Solving time ~10min)

Assume transistors M1, M2, M3 are in biased in saturation, and transconductances of the transistors M1, M2, and M3 are gm1, gm2, and gm3 respectively. Ignore channel length modulation, i.e., λ = 0 for all transistors.

A. Calculate the small signal gain (𝑣𝑜𝑢𝑡/𝑣𝑖𝑛) in terms of gm1, gm2, gm3 and RL. (10 points)

B. For a given biasing point, gm1 = 1mS, gm2=0.5mS, gm3 = 1mS, and RL = 2KΩ, and small signal input, 𝑣𝑖𝑛 = 0.1*sin(100*t)-0.3*cos(200*t), where t represents time. Calculate the average power dissipated in load resistor RL due to this small signal input. (5 points)

Hint: Rms value of A*sin(ωt) is A/.

Problem 6 (25 points): (Solving time ~20min)

NMOS: µn = 400 cm2/V⋅s, Cox = 4×10-7 F/cm2, Vthn = 1 V, λn = 0.1 PMOS: µp = 100 cm2/V⋅s, Cox = 4×10-7 F/cm2, Vthp = -1 V, λp = 0.2 For the amplifier circuit shown below, assume:

· Iref = 0.2mA,

· (W/L)1 = 1m/0.5m, (W/L)2 = 5m/0.5m, (W/L)3 = 5m/0.5m,

· Rin = 10KΩ, and RL = 5 KΩ.

· All capacitors C1, C2 and C3 are very large and their effect is negligible in small signal circuit.

A. Calculate value of IDS of M3. (4 points)

B. Calculate gm1, gm2 and gm3. (6 points)

C. Calculate value of R1 such that small signal gain is not effected by R1. (When A<<B, consider 100*A = B). (5 points)

D. Calculate value of Rf such that small signal gain is not effected by Rf. (When A<<B, consider 100*A = B). (5 points) E. Calculate small signal gain. (5 points)

1

of

4

1

of

4

1

of

4

Electrical Engineering homework help

192 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Single-Stage High-Efficiency 48/1 V Sigma
Converter With Integrated Magnetics

Mohamed H. Ahmed , Student Member, IEEE, Chao Fei , Student Member, IEEE,
Fred C. Lee , Life Fellow, IEEE, and Qiang Li , Member, IEEE

Abstract—A high-efficiency, high-power-density Sigma
converter for a 48 V rack architecture in data centers is
proposed in this paper. The Sigma converter is a quasi-
parallel converter that uses a high-efficiency unregulated
converter to deliver the bulk power to the load. A small
buck converter is responsible for regulating the output volt-
age with prescribed dynamic responses. A design guideline
for Sigma converter with integrated magnetics is provided
in this paper. The unregulated converter is an LLC con-
verter designed with a printed circuit board (PCB) winding
matrix transformer, a structure which integrates four ele-
mental transformers into one core. The buck converter is
designed with discrete gallium nitride (GaN) devices and a
PCB winding inductor. The proposed Sigma converter op-
erates at 48 V input and 1 V-80 A output and can achieve a
power density of 420 W/in3 as well as a peak efficiency of
94%.

Index Terms—48 V voltage regulator module (VRM),
integrated magnetics, matrix transformer, Sigma converter.

I. INTRODUCTION

D UE TO the ever increasing load demands of data centersand telecommunication applications, a 10% share of the
total power consumption by 2020 [1] is predicted. These needs
are driving the power management solutions for increased
efficiency and power density. To fulfill digital content demands,
multicore processors with a greater number of cores and power-
hungry processors are increasing every year. With increasing
demands of high current (>220 A) at low voltage levels
(<1.85 V) for each CPU [2], the power consumption per server
rack is reaching 15 kW. This raises attention toward a more
efficient system architecture in the rack level. Traditionally,
data centers the system architecture as shown in Fig. 1(a) with
a 12 V bus backplane, thus, resulting in poor overall power
delivery efficiency due to the large distribution loss at the 12 V
bus. Shifting to higher bus voltages, 48 V instead of 12 V, was
proposed [3], and subsequently adopted, by Google as shown
in Fig. 1(b), where the uninterruptible power supply (UPS)

Manuscript received March 25, 2018; revised July 10, 2018, August
28, 2018, and November 15, 2018; accepted January 6, 2019. Date of
publication February 5, 2019; date of current version August 30, 2019.
(Corresponding authors: Mohamed H. Ahmed and Qiang Li.)

The authors are with the Center for Power Electronics Systems,
Virginia Polytechnic Institute and State University, Blacksburg, VA
24061 USA (e-mail:, mohamed4@vt.edu; feichao@vt.edu; fclee@vt.
edu; lqvt@vt.edu).

Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2019.2896082

Fig. 1. Data centers distribution system: (a) traditional ac distribution;
(b) dc distribution with 48 V bus.

systems are replaced by a local dc 48 V battery backup [4].
Significant challenges rise with that proposed architecture. The
48 V voltage regulator module (VRM) located in the vicinity
of the CPU has to be designed with very high efficiency and
high power density [5].

A great amount of work has been done with the 48 V VRM
for both data center and telecommunication applications. They
can be categorized as one-stage and two-stage solutions.

A two-stage 48 V VRM is the first commercially avail-
able solution by Vicor [3], [6]. Their soft-switched first-stage
buck-boost preregulator module (PRM), cascaded with a soft-
switched unregulated sine amplitude voltage transformation
module (VTM), enables their solution to achieve high efficiency
and high density. However, the solution is not easily scalable as
designed in high current levels (>100 A/module). Another two-
stage approach was used in [5], [7], and [8], with an unregulated
inductor-inductor-capacitor (LLC) dc–dc transformer (DCX) as
the first stage and a conventional multiphase regulated buck
converter for the second stage. This solution reported a high ef-
ficiency and high density with significant improvement for light
load efficiency. The two-stage architecture was proposed in [4]
and [9], replacing the isolated bus converters with a resonant
switched capacitor circuit that can achieve a high efficiency
of 98.2% and power density of 500 W/in2 for the first stage
converter; however, there is no reported two-stage efficiency or
power density for the 48/1 V conversion. Another state-of-art
product was proposed by STM Microelectronics [10] based on
a single-stage quasi-resonant converter with a current-doubler
rectifier reported in [11] and [12]. The converter can operate with
zero voltage switching (ZVS) in all loading conditions with a
high efficiency of 93%. However, the topology requires four
magnetic components, reducing the converter power density. In

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 193

Fig. 2. Sigma converter structure.

[13]–[15] a current-tripler 48 V VRM with a compact mag-
netic structure was proposed, together with a 1-MHz self-driven
scheme that solves the problem of synchronous rectifier (SR)
switching and can achieve very high efficiency at high-frequency
operation. However, in the proposed scheme not all the primary
side switches can achieve ZVS at light load, resulting in a sig-
nificant efficiency drop during light loading conditions.

The Sigma converter concept was first proposed in [16] and
[17], for 12 V VRMs that exhibited outstanding performance
over multiphase buck converters. The same architecture was
later used in different applications [18], [19] demonstrating a
very efficient operation. In this paper, the same concept was
revisited and proposed for a single-stage 48 V VRM [20]. The
Sigma converter is a quasi-parallel converter that connects two
converters in series from the input side, and in parallel from
the output side. One of the converters is an unregulated isolated
DCX that conducts the bulk power, while the other is a non-
isolated converter responsible for regulating the output voltage
(D2D), as shown in Fig. 2. A potential benefit of this architecture
is its ability to achieve higher conversion efficiency.

Further efforts should be made for the design of the DCX
and D2D to maximize the benefits of this power architecture.
The soft switching properties of the LLC converter enables
operation at a very high frequency to achieve high density while
achieving high efficiency, making it a suitable candidate for this
converter’s DCX. Integrating magnetics with PCB winding and
matrix transformer with the opportunity of flux cancellation has
been reported [21]–[27] to reduce the size and losses of the LLC
DCX transformer at high-frequency operation.

None of the preceding work has discussed the Sigma con-
verter design with integrated magnetics even though the matrix
transformer structure and design will impact the performance of
this converter significantly as will be discussed in the following
sections. In this paper, a detailed design guideline for the Sigma
converter with integrated magnetics will be discussed by which
the right matrix transformer structure can be chosen for differ-
ent input/output voltage variations to maximize the benefits of
this conversion system. A novel matrix transformer which inte-
grates four elemental transformers into one core structure with
printed circuit board (PCB) windings is proposed to achieve
high efficiency and power density. Accompanying the DCX is
a buck converter with PCB winding inductor to realize all the
stringent requirements for regulation dynamics while increasing
the power density.

TABLE I
PROPOSED CONVERTER SPECIFICATIONS AND LLC-DCX TURNS RATIO

DESIGN RANGE

This paper is organized as follows. Section II presents the
design principle of the Sigma converter architecture with inte-
grated magnetics. Section III discusses the optimal design of the
LLC-DCX with a PCB winding matrix transformer. Section IV
optimizes the design of the buck converter with a PCB wind-
ing inductor. Section V presents the converter prototype and the
experimental results. Section VI concludes this paper.

II. DESIGN GUIDELINE OF SIGMA CONVERTER WITH
INTEGRATED MAGNETICS

In the Sigma architecture, both converters have the same input
current, thus, the power sharing between them is proportional to
the input voltage across each of them as in (1). In the proposed
architecture, the DCX converter is an LLC converter operating
at resonant frequency, utilizing the matrix transformer’s leak-
age inductance to form the resonant tank with the addition of
resonant capacitor. The small leakage inductance of the matrix
transformer will result in a large Ln = Lm /Lr resulting in a
constant gain LLC converter that does not change much with
frequency variation. As a result, the input voltage of the DCX
will be the output voltage of the converter multiplied by the
DCX turns ratio n and the remaining voltage will appear on the
buck-D2D as given in (2). The DCX turns ratio n has a signifi-
cant role in the voltage distribution across these two converters
and consequently, the power sharing among them. For efficient
power conversion, the LLC-DCX is required to handle most of
the power as it can be designed with very high efficiency com-
pared to the buck-D2D; the condition VDCX � VD 2D should
be satisfied in order to achieve that goal.

The Sigma architecture has two main design constraints—
the first constraint is to achieve high efficiency of operation
by limiting the maximum allowable voltage appearing on the
buck converter during all operating conditions, this constraint
limits the minimum allowable turns ratio as given in (3). The
second constraint is to ensure a positive voltage across the buck
converter that is always higher than the maximum output voltage
by which the duty ratio is always (D < 1) and this condition
is given by (4) and sets the maximum allowable turns ratio.
Vinm in , Vinm ax , Vom in , Vom ax are the maximum and minimum
input and output voltages, respectively, Dm ax is the maximum
buck duty ratio, and Vbuckm ax is the maximum stress on the
buck converter.

Different applications will require a specific design of this
architecture based on the constraints mentioned above. The pro-
posed converter specifications and the turns ratio design range
are listed in Table I. The maximum allowable voltage across
the buck converter is set to be Vbuckm ax < 30 V , this will allow

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194 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 3. (a) Basic matrix transformer structure with multiple elemental
transformer. (b) Primary winding implementation with PCB winding.

using low voltage devices for the buck converter to maximize
its efficiency and maintain the bulk power to flow through the
LLC-DCX in all operating conditions

PDCX /PD 2D = VDCX /VD 2D (1)

VDCX = nVo VD 2D = Vin − nVo (2)

nm in >
Vinm ax − Vbuckm ax

Vom in
(3)

nm ax <
Vinm in
Vom ax

− 1
Dm ax

. (4)

Although the maximum turns ratio (nm ax = 43) will result in
the most efficient operation, the implementation of specific turns
ratio with matrix transformer is constrained by other limiting
factors. First, the matrix transformer with core simplification and
integration by the flux cancellation method has been proposed
in [21] and [25] by which two elemental transformers can be
integrated using a single UI-core, resulting in significant core
loss and footprint reduction. This means that we always need
an even number of elemental transformers (2, 4, 6, . . . , etc.)
in order to take the advantage of flux cancellation and core
integration for high efficiency and power density.

Second, the basic structure of matrix transformer with
multiple elemental transformers is shown in Fig. 3(a), where
the single transformer is divided into multiple elemental
transformers connected in series from the primary side and
in parallel from the output side. To ensure equal current
sharing between these elemental transformers, the number
of turns in each elemental transformer should be equal, i.e.,
(nTR1 = nTR2 = . . . = nTRN ). Third, with the requirement
of multiple turns per elemental transformer (nTRx > 1), these
turns should be implemented in more than one layer in order
to have an entrance and exit path for the primary side current
without using extra via or PCB layers as shown in Fig. 3(b).
Finally, the number of primary turns per PCB layer should be
equal in order to maintain a balanced magnetomotive force
(MMF) across the transformer winding and ensure perfectly
interleaved primary and secondary windings to reduce all
ac-related winding loss.

Applying these four PCB winding implementation related
constraints to the design specifications and architecture
constraints listed in Table I will result in all the design options

TABLE II
LLC-DCX WITH MATRIX TRANSFORMER OPTIONS FOR SIGMA CONVERTER

WITH DIFFERENT PRIMARY SIDE CONFIGURATIONS

Fig. 4. Proposed 48/1 V-80 A Sigma converter structure.

listed in Table II, where, NE is the number of elemental trans-
formers, nTR is the turns ratio of each elemental transformer,
and ntotal = NE × nTR is the LLC-DCX total transformer
ratio.

It is clear that different matrix transformer and primary side
configurations will have different impact on the Sigma converter
operation, the first and last options NE = 4 and NE = 10 will
result in the highest possible converter efficiency with the high-
est power flowing through the LLC-DCX. Although both have
the same impact on the architecture, for simplicity of the design,
the first option (NE = 4 )was chosen for this design, the case
with NE = 10 can be a possible candidate if a higher current
converter is required. Although half bridge (HB) configuration
have lower turns ratio, it requires more PCB layers compared to
the full bridge (FB) configuration to implement the PCB wind-
ing, so FB was selected to reduce the cost and complexity of the
proposed converter. The proposed Sigma converter structure is
shown in Fig. 4, the total DCX turns ratio is n = 40 : 1. The
benefits of this design can be shown from the power-sharing
graph in Fig. 5. At most operating conditions, the LLC-DCX
handles most of the output power by which higher overall ef-
ficiency is expected. The same design guidelines can be used
for other 48 V VRMs with different input and output voltage
and power requirements to select the optimal matrix transformer
structure for each application. The optimization of this matrix
transformer will be discussed in the following section to achieve
the highest possible efficiency and power density.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 195

Fig. 5. Power sharing between the LLC-DCX and the buck-D2D.

III. LLC CONVERTER WITH MATRIX TRANSFORMER DESIGN
AND OPTIMIZATION

The design of LLC-DCX for high output current and low
output voltages is very challenging. The necessity of paralleling
multiple SRs to handle this high output current results in cur-
rent sharing problems and large transformer termination losses,
a practice that should be avoided if possible. The concept of the
matrix transformer is to employ various elemental transformer
arrays interwired to form a single transformer. This will re-
duce the total transformer losses by splitting the current among
various elemental transformers and in the same time achiev-
ing flux cancellation wherever possible. The matrix transformer
has exhibited an outstanding performance when used in various
applications. In addition to minimizing termination losses, the
simple PCB winding implementation makes it suitable for this
application, where high output current of the LLC-DCX is re-
quired. In this section, the design and optimization of the matrix
transformer for the LLC-DCX will be discussed in detail.

A. Integration of LLC-DCX Matrix Transformer Structure
and PCB Winding Implementation

For the proposed Sigma converter, the LLC-DCX requires
a transformer with (40:1) turns ratio. This single transformer
was broken into four elemental transformer arrays as shown
in Fig. 6, where the transformer leakage and magnetizing in-
ductances with an additional capacitor are used to form the
resonant tank of the LLC-DCX. The primary windings of this
structure are connected in series while the secondary windings
are connected in parallel. Hence, there would be no current shar-
ing problem between paralleled secondary windings or SRs. To
further reduce conduction losses, the proposed structure par-
allels only two SRs at each secondary winding. Transformer
termination is the physical connection between the transformer
windings and the corresponding primary and secondary devices.
They contribute to a large portion of the transformer losses when
operating at high switching frequencies [21]. The matrix trans-
former structure helps split the output current among different
transformer outputs, thus reducing conduction and termination
losses significantly.

Fig. 6. Proposed LLC-DCX with matrix transformer.

A potential drawback of the matrix transformer approach is
the increased footprint and core loss due to the increased number
of magnetic cores. By operating at very high switching frequen-
cies, the magnetic core size can be reduced. To achieve high
power density, the complex four-transformer structure shown
must be simplified. Originally, the four elemental transformers
each utilize a separate UI-core as shown in Fig. 7(a). By rear-
ranging the four transformers in a way that two transformers
are on the top side (TR1 and TR2) and two on the bottom side
(TR3 and TR4) we can integrate the four transformers with one
core structure with a wide center leg as the return flux path of
each elemental transformer as in Fig. 7(b). By reversing the cur-
rent direction in TR3 and TR4, the flux in the wide center leg
will be in opposite directions and cancel each other, reducing
the total core loss and allowing the removal of this center leg
without scarifying any winding or core loss. Hence, the four
transformers can be integrated into one core structure with four
transformer pillars, which can be easily manufactured, saving a
significant amount of space and core loss as shown in Fig. 7(c).
The proposed integration method not only helps with the reduc-
tion of the core loss and footprint but also helps in achieving a
perfectly current sharing between all the transformer secondary
windings. Integrating the four transformers into a single core
structure helps achieve a symmetrical air gap for all the four el-
emental transformers. Although the four primary windings are
connected in series, each elemental transformer will see a differ-
ent magnetizing inductance determined by its own air gap; any
asymmetry in the magnetizing inductances between these ele-
mental transformers will create a current unbalance between the
secondary windings as well. With the single core structure, the
tolerance in these air gaps can be well-controlled to avoid these
problems when compared to using two single UI-cores [25].

The proposed matrix converter is implemented with a 14-layer
PCB and 2 oz copper for each layer. The detailed PCB winding
arrangement is shown in Fig. 8, the yellow arrows indicate the
current directions in the positive half-cycle. Layers 1 and 14 are

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196 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 7. Derivation of proposed matrix transformer: (a) original four ele-
mental transformer structure with separate UI-cores; (b) rearranged four
elemental transformers integrated in one core with a wide center leg;
and (c) integrated matrix transformers with one core structure without
center leg.

used to place the SRs and the output capacitors. Each set of paral-
lel SRs have one device on Layer 1 and the other device on Layer
14. These devices and capacitors are then connected to the cor-
responding secondary winding through vias. This arrangement
helps reduce the termination connections between windings and
SRs, while splitting the termination current into two layers. This
reduces termination losses significantly. Layers 3 and 6 are one
set of primary windings. In each layer, five turns are wrapped
around each core pillar and then both layers are connected in se-
ries, totaling the required 40 turns. A parallel connection is made
with Layers 9 and 12, which is another set of primary windings
to reduce conduction losses. The remaining layers are for the
center-tap secondary windings. Each layer has one turn, and all
layers are in parallel, to reduce conduction losses. The primary
and secondary windings are perfectly interleaved to reduce the
ac losses due to the proximity effect as shown in Fig. 8(b).

B. Matrix Transformer Design Optimization

To optimize the matrix transformer design, the tradeoff be-
tween total transformer losses and the footprint is evaluated, and
then the optimal switching frequency is selected. First, the im-

Fig. 8. PCB winding arrangement of the proposed matrix transformer:
(a) Layers 1&14 for SRs and output capacitors. (b) 14 layer PCB
arrangement. (c) Layers 3 and 9 for primary#1 windings. (d) Layers 6 and
12 for primary#2 windings. (e) Layers 2, 5, 8, and 11 for secondary#1
windings. (f) Layers 4, 7, 10, and 13 for secondary#2 windings.

TABLE III
CORE SHAPE IMPACT ON WINDING LOSS

pact of the core pillar shape on the winding losses was evaluated.
A rectangular core versus a circular core pillar was evaluated
by finite-element analysis (FEA) simulations; both cases have
the same core area and winding width. The results in Table III
show a 16–22% winding loss reduction with the circular post
due to the shorter current path length. Secondly, various high
frequency magnetic materials were previously surveyed in [5]
and the results showed that the ML-91 from Hitachi shows the
lowest core loss density for this high-frequency operation and
therefore, it was selected for the proposed LLC-DCX converter.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 197

Fig. 9. Transformer total losses and footprint at 1.5 MHz and full load.

Fig. 10. Transformer losses variation with switching frequency.
(a) Winding loss. (b) Core loss.

The design optimization of matrix transformer has been dis-
cussed in previous literature [23]–[25] for 400/12 V converters,
the total transformer loss is calculated at the optimal footprint
and then a design point is selected as a tradeoff between effi-
ciency and power density. The same design methodology was
used for this transformer by adding a new design parameter,
which is the operating switching frequency; the total trans-
former losses versus optimal footprint at full load and nominal
voltage conditions at 1.5 MHz switching frequency are shown
in Fig. 9. Due to the low output voltage and high frequency, the
volt·second applied on the core is very small, and the winding
losses are more dominant with very small core losses.

With lower switching frequencies, the ac related winding
loss will reduce, while the core loss increases due to the higher
volt·second as shown in Fig. 10. From the results in Fig. 11,
the total losses are highest at high switching frequencies, when
reducing the frequency, a reduction in the total losses occurs
until 1 MHz is reached. This is because the reduction in the
winding losses is counteracted by a significant increase in the
core losses, so further reducing the switching frequency will
result in a higher total transformer loss.

To achieve high efficiency and power density, the design re-
gion is highlighted in Fig. 11. The corresponding total loss vari-
ation with different switching frequencies was plotted as shown
in Fig. 12. With different footprints, the total losses tend to have
a minimum loss point at 1 MHz switching frequency; therefore,
1 MHz was selected as the operating frequency. The efficiency
of the converter was then calculated, and the final design point

Fig. 11. Transformer total loss versus footprint at different switching
frequencies.

Fig. 12. Transformer total losses versus switching frequency.

Fig. 13. Transformer fringing flux impact. (a) Cross-sectional view of
fringing flux distribution. (b) Current distribution in Layer 1. (c) Current
distribution in Layer 14.

was selected at a footprint of 300 mm2, since after that point,
the increase in the converter efficiency is marginal.

The magnetizing inductance of the transformer is created by
adding an air gap between the core pillar and the magnetic plate.
A great amount of fringing flux will spread through the air gap
creating many eddy current losses in the nearby layers. This
could be severe for the designed transformer. The fringing flux
at the air gap was simulated using ANSYS Maxwell and the
results shown in Fig. 13 show the strong fringing flux at the air
gap of one of the four elemental transformers. Layer 14, which
is closer to the air gap, handles the same amount of current,
but has ten times more losses than Layer 1. This is due to the

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198 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 14. Total transformer losses versus extending the core air gap.

TABLE IV
PARALLEL LAYER CURRENT DISTRIBUTION

strong fringing flux. To solve this issue, the air gap needs to
be pushed away from the PCB layers by a distance hf r . Using
FEA simulation, different hf r values were evaluated, and the
results are shown in Fig. 14. The total loss reduced significantly
with the higher hf r , until reaching a diminishing return point at
hf r = 0.6 mm, which was chosen in the final design.

In the proposed PCB winding arrangement shown in Fig. 8(b),
we have two primary parallel layers and four secondary winding
parallel layers. Although we minimized the losses due to the
fringing flux, it tends to attract the current to the layers close
to the transformer air gap resulting in an unbalanced current
sharing as listed in Table IV. This issue has not been addressed
in this paper and more analysis needs to be done in order to have
perfect current sharing between layers.

IV. BUCK CONVERTER DESIGN OPTIMIZATION WITH PCB
WINDING INDUCTOR

The Sigma converter was designed so that most of the power
flows through the higher efficiency LLC-DCX while the buck
converter is responsible for regulating the output voltage. From
Fig. 5, it is clear that the power and voltage applied to the buck
converter is variable, depending on the operating condition. In
the worst case (Vo = 0.8 V and Vin = 55 V), the buck con-
verter will experience a voltage stress of (Vbuckm ax = 23 V)
and should handle a current of about (33 A), so devices with a
minimum voltage rating of 40 V are required for the buck con-
verter. Low voltage gallium nitride (GaN) devices have shown
an outstanding performance compared with silicon devices. In
this design, the high side switch is EPC2015c while the low
voltage switch is EPC2024. An optimal layout presented in [28]
was used for the layout of the discrete GaN devices to minimize
the effect of parasitic inductances and their effect on switching
related losses. The inductor design for this buck converter is

Fig. 15. Proposed single-turn PCB winding inductor structure: (a) top
view and (b) cross sectional view.

Fig. 16. Measured efficiency of buck converter with discrete inductor
and PCB winding inductor.

important to achieve high power density and high efficiency.
For low voltage buck converters, the common practice is using
a commercial discrete inductor that has a very low dc resistance
(DCR) and low core loss. However, these inductors have a large
footprint and high profile, which reduces the overall converter
power density significantly.

In this proposed Sigma converter, the LLC-DCX uses a
14-layer PCB to implement the DCX transformer. The same
PCB can be utilized to implement a single-turn inductor. As the
PCB copper thickness is smaller than the copper foil thickness
used by discrete inductors, the inductor windings can be parallel
connected in multiple layers, to reduce the total inductor DCR.
The basic structure of the proposed PCB winding inductor is
shown in Fig. 15. An EI-core shape with ML-95 material from
Hitachi was used to implement the single-turn inductor. An in-
ductance of L = 190 nH and a DCR of RDC = 0.53 mΩ are
achieved. Although the DCR in the proposed design is larger
than the commercial discrete inductors, the efficiency reduc-
tion is negligible since the buck converter is only handling a
small amount of output current. Using this PCB winding induc-
tor will help achieve high power density without scarifying the
efficiency. A buck converter with commercial discrete inductor
and PCB winding inductor was experimentally evaluated. The
measured efficiency shown in Fig. 16 shows that the buck con-
verter with PCB winding inductor has higher efficiency in most
operating regions.

The reason for this is the lower core loss of the designed PCB
winding inductor; the ac-related loss of the PCB winding in-
ductor was evaluated using ANSYS Maxwell. The commercial
inductor used is from Würth Elektronik, and the ac-related loss
of this inductor was calculated based on the inductor loss cal-
culator software REDEXPERT. It can be shown from Table V
that the ac-related losses of the PCB winding inductor is three
times lower than that of the commercial inductor. These losses

Electrical Engineering homework help

Title

TABLE OF CONTENTS

(
ii
i
)

Abstract 1
Problem Statement. 2
Need: 2
Objective: 2
Background and Technology Survey: 2
Radar System 3
Basic DDS: 4
Possible Implementations of DDS: 4
Profile Definition 5
Anti-Alias Filter: 5
JTAG: 7
Needs Identification 7
Marketing Requirements 7
List of Marketing Requirements: 7
Objective Tree: 8
Ranked Needs: 8
Requirements Specifications 10
The Requirements 10
Engineering Requirements: 11
Engineering Requirement #: 1 11
Engineering Requirement #: 2 12
Engineering Requirement #: 3 13
Engineering Requirement #: 4 14
Engineering Requirement #: 5 15
Engineering Requirement #: 6 16
Engineering Requirement #: 7 17
Engineering Requirement #: 8 18
Engineering Requirement #: 9 19
Engineering Requirement #: 10 20
Engineering Requirement #: 11 21
Engineering Requirement #: 12 22
Constraints: 23
Economic: 23
Environmental: 23
Manufacturability: 23
Health and Safety: 23
Social. 23
Standards 23
Testing. 23
Communications 23
Documentation 23
Design 24
Design Alternatives: 24
Control Unit: 24
3.1.2. LCD: 25
3.1.3. Direct Digital Synthesizer: 25
Level 0: 26
Level 1: 27
Level 2: 30
System Flow Chart 30
Finite State Machines: 33
User Interface: 33
Liquid Crystal Display: 34
Direct Digital Synthesizer 34
Low Pass Filter: 35
Enclosure: 37
Circuitry: 38
3.4.5.1. AD9858: 38
Spartan 3 FPGA: 39
Power Supply: 40
User Interface Circuitry 41
Phase Lock Oscillator: 43
Design Verification. 44
Test Results: 44
Low Pass filter: 44
Evaluation Boards: 45
Printed Circuit Board: 48
Final Verification: 49
Requirements Verification: 50
Requirements Verification Chart 50
Summary and Conclusions. 51
Conclusion 51
Further Improvements 51
References: 52
Appendix A: Project Management Plan 53
Appendix B: Software. 56
Appendix C: Definitions and Acronyms/Abbreviations 58

FIGURES

Figure 1: Basic Radar System Block Diagram 3

Figure 2: A basic DDS system 4

Figure 3: Filter cut off response [2] 6

Figure 4: JTAG daisy chained circuitry 7

Figure 5: Objective trees for the DDS waveform generator 8

Figure 6: Level 0 Diagram 26

Figure 7: Level 2 System Flow Chart 30

Figure 8: Level 2 Button FSM 33

Figure 9: Level 2 LCD FSM 34

Figure 10: Level 2 AD9858 FSM 35

Figure 11: Level 2 LPF Circuitry. 36

Figure 12: Level 2 LPF Simulations 36

Figure 14: Level 2 Enclosure 37

Figure 15: Level 2 Front Panel 37

Figure 16: Level 2 AD9858 Circuitry 38

Figure 17: Level 2 Spartan 3 Circuitry 39

Figure 18: Level 2 Power Supply Design 40

Figure 19: Level 2 Vregs Circuitry 41

Figure 19: User interface 42

Figure 20: ARTEMIS Phase Lock Oscillator 43

Figure 21: Seven Section Chebyshev Low Pass Filter 44

Figure 22: Network Analyzer Verification 45

Figure 23: Analog Device’s AD9858 Evaluation Board 46

Figure 24: Digilent’s Spartan 3 FPGA evaluation board [4] 46

Figure 25: AD9858 interface with Spartan 3 47

Figure 26: Spectrum Analyzer Verification 47

Figure 27: 5 Layer Printed Circuit Board 48

Figure 28: Output Frequency Verification 49

Figure 29: Work Time line. 53

Figure 30: Work Breakdown Structure 54

TABLES

Table 1: Pairwise Comparisons Matrix – General 8

Table 2: Pairwise Comparison – Ease of Use 8

Table 3: Pairwise Comparison – Frequency Capability 9

Table 4: Pairwise Comparison – Portability 9

Table 5: Marketing Requirements to Engineering Requirements Mapping 10

Table 6: Control Unit Strengths and Weakness 24

Table 7: LCD strengths and weakness 25

Table 8: DDS strengths and weakness 26

Table 9: Level 0 DDS Signal Generator 27

Table 10: Level 1 AD9858 DDS chip. 27

Table 11: Level 1 Power Supply 28

Table 12: Level 1 Anti-Aliasing Filter. 28

Table 13: Level 1 Control Buttons. 28

Table 14: Level 1 LCD 28

Table 15: Level 1 FPGA [5] 29

Table 16: Requirements Verification Chart 50

Table 17: Part List 55

Abstract

The purpose of the project is to create a continuous wave (CW) analog signal generator for Advanced Radar Techniques Equipment Microwave Integrated Systems (ARTEMIS) Inc. It will be used to simulate a direct digital synthesizer (DDS) used in Synthetic Aperture Radar’s (SAR). This device will replace the expensive, long lead time and custom designed DDS’s.

The analog signal generator will synthesize a sinusoidal wave. Its frequency will be adjustable and be provided to the user via SubMiniature version A (SMA) connection.

(
10
)

1. Problem Statement

1.1. Need:

Advanced Radar Techniques Equipment Microwave Integrated Systems (ARTEMIS) Inc. needs a low cost, low frequency analog signal generator. This device will help solve their signal generator shortage and save the company money. Generators on the market today are very expensive with many features that are not needed. ARTEMIS would like a simple signal generator that will meet their needs. This generator will be used in their upconverter test setup. This test setup requires a 0 MHz to 300 MHz analog input signal used in the upconverter’s translation and generation of transmit (TX) and local oscillator (LO) signals. The test setup consists of a few high frequency, one low frequency generators and a spectrum analyzer.

1.2. Objective:

Our objective is to design a portable low cost analog signal generator using the Direct Digital Synthesis technique specified by the company. This device will have a user interface that will allow the user to interactively set the output frequency. The generator’s output must be available via SMA female connectors for easy access by the user. The device will also have multiple profiles. Each profile will allow the user to set and recall a particular frequency.

1.3. Background and Technology Survey:

Most signal generators on the market today (in the range of 0-300MHz) cost anywhere from

$800 to $2,000 dollars and above. [1] These generators are designed to meet the needs of many different customers and therefore support a wide range of functions and special features. Many of these extra features are not needed and will not be implemented in our design. Due to limited resources, the signal generators at ARTEMIS are shared among multiple test setups. This is an inconvenience and can cause delays in system testing. The company cannot justify buying separate generators for each test setup when only some of the features will be utilized. Our task is to design a low cost signal generator for ARTEMIS that doesn’t include unnecessary (and costly) features. The signal generator will be designed to output a variable sinusoidal frequency. This signal will be used as a reference for the (Direct Digital Synthesis) DDS signal. The upconverter is one of ARTEMIS’s products used for translation and generation of TX and LO signals. The TX and LO signals are generated by up converting its input signals to a high frequency radio signals.

1.3.1. Radar System:

Figure 1 shows a basic radar system block diagram. The overall function of the DDS is to generate a chirp. A chirp is a quick frequency sweep. The chirp is sent through the upconverter where it is up converted to a microwave frequency. The microwave frequencies are then amplified by the SSPA (Solid State Power Amplifier) and transmitted out of the antenna. The system is then switched to receive mode where the reflected signals are captured by the antenna and sent into the receiver. The receiver then down converts the signals and sends it to a digitizer. The digitizer uses an ADC (analog to digital converter) to convert the signal into a digital representation of the reflected signal. The data is then sent to the digital signal processor to extrapolate the image.

Our waveform generator will be replacing the DDS subsystem during ARTEMIS’s testing phase. It will be used to supply an analog signal to the upconverter. Each fundament frequency of the upconverter is tested and tuned to the desired level.

Figure 1: Basic Radar System Block Diagram

1.3.2. Basic DDS:

Figure 2: A basic DDS system

The basic function of a Direct Digital Synthesizer is straightforward. A lookup table holds a digital representation of the desired waveform over one period, with each row of the table containing a sample of the waveform’s amplitude. A system controller steps through this lookup table at a specific rate, feeding its value of the current row to the input of a DA (digital to analog) converter. When the controller reaches the end of the lookup table it cycles back to the first row and repeats the process. This process results in the desired analog signal appearing on the output of the DAC. Since no time consuming calculations are needed during signal generation this is a notably fast technique. The output frequency can be changed by altering the values in the lookup table or reading from a separate lookup table

1.3.3. Possible Implementations of DDS:

There are multiple ways to implement a DDS system. One possibility is to directly build the DDS shown above using standard logic components. Alternately, a DDS system could be developed using a FPGA (Field Programmable Gate Array). Finally, a dedicated DDS SOC (system on a chip) could be used. Each of these implementations has advantages and disadvantages as discussed below.

Designing the system using standard logic components such as RAM memory, a micro- controller, DA converter, counter, etc would allow for a great deal of design flexibility. We would be able to choose precisely what features would be included in the design and not have to pay for other features that wouldn’t be necessary. For this reason, this implementation is likely to be the cheapest of the three. One disadvantage to this solution, however, is that the design would be very complex. Extensive consideration would be required to ensure that the device could achieve the frequency range and frequency resolution specified by ARTEMIS. Also, we

could easily be “reinventing the wheel” by using this method since there are dedicated DDS chips on the market that might have the same functionality.

Using a FPGA to realize a DDS system would provide a moderate amount of design flexibility, although not as much as a basic component-based system. This implementation would reduce design complexity, since FPGAs can easily be reprogrammed and thus different design solutions could easily be tested and compared to one another. Some components may be required in addition to the FPGA, but this solution will still be much simpler than the previous one. As with the basic component-based system, this design work would be unnecessary if there is a pre-built DDS chip on the market that exhibits the functionality desired.

A dedicated DDS chip can have all of the system components integrated onto a single chip. Although designing a dedicated chip ourselves is beyond the scope of this course there are many DDS chips currently on the market that might be appropriate for this project. This method provides minimum design flexibility since we would be limited to the features already designed into the chip. However, if we find a chip that satisfies our project requirements, this will be a very viable option.

Another possible choice is to use an FPGA with a soft core. With this method, the FPGA is configured to operate as a reduced instruction set (RISC) processor. Software can then be written for this processor in assembly or even the C programming language. We would then write a program to implement a DDS system and load it onto the FPGA/RISC processor.

1.3.4. Profile Definition:

One of the marketing requirements below is that the device must be able to store and restore waveform settings. Throughout this document, we refer to the collection of all waveform settings that describe a particular output, as a profile. The user will be able to manipulate waveform settings until the desired output is achieved and then store these settings in a user profile. This profile may then be selected at a later time to restore the output waveform that was stored earlier.

1.3.5. Anti-Alias Filter:

At the output of the DSS signal an anti-aliasing filter is needed to reconstruct the analog signal. During the Direct Digital Synthesis, aliases are created and need to be removed from the output waveform. These aliases are created since the direct digital synthesis system is a sampled data system. The aliases occur when frequency components are greater than half the sample rate.

There are four different types of filters (Elliptic, Chebyshev, Butterworth, and Bessel) that can be used to remove these aliases. Below in figure 3 is a diagram of the four different types of filters and their cut off response.

Figure 3: Filter cut off response [2]

If you look to the left of the vertical dotted line this is the pass band. This is the area in which the signals are allowed to pass. To the right of the vertical dotted lines is the stop band this is the area in which signals are rejected. If you look at the individual filter curves your see a slight ripple on a few of the responses. This is the attenuation (decreased power level) of the signal.

We will be choosing a filter that will have a sharp enough transition to allow want signals through and reject unwanted signals. We also have to take into consideration a filter with the least amount of attenuation. With the help of ARTEMIS and an application called Microwave Office we will be designing a filter to meet our needs. The designed filter will likely be either an Elliptic or Chebyshev filter with multiple segments to handle a wide range of frequencies.

1.3.6. JTAG:

JTAG is an acronym for Joint Test Action Group. Its standard entitled Standard Test Access Port and Boundary-Scan Architecture is used for testing circuit boards via boundary scan. It can also be used as a programming protocol. This five-pin interface is designed so that all onboard chips have the JTAG lines daisy chained together as shown in figure 4. This allows for access to all the onboard chips. The five-pins (TMS, TCK, TRST, TDI, and TDO) are defined as follows.

(
TDI
TDO
TDO
TDI
DEVICE

2
TMS
TCK

TRST
TDO
TDI
DEVICE

1
TMS
TCK

TRST
)TMS

TCK

TRST

Figure 4: JTAG daisy chained circuitry

TMS stands for Test Mode Select this is used to determine the next state. TCK is Test Clock which synchronizes all of the internal finite state machine operations. TRST stands Test Reset this resets the internal finite state machine. TDI and TDO are the Test Data In and Out. If you could imagine a giant shift register this is how the TDI and TDO work. The Data is pushed into the TDI and shifts everything to the right and the last bit is pushed out the TDO. This protocol has a lot of advantages and can be used for in-circuit debugging, flashing on board chips, and chip identification.

1.3.7. Needs Identification

1.3.7.1. Marketing Requirements

1.3.7.1.1. List of Marketing Requirements:

The system should:

· Have fine frequency resolution.

· Have outputs available on SMA female connectors.

· Be able to generate a wide range of output frequencies.

· Be able to store and restore waveform settings.

· Have an easy to use interface.

· Be small, portable and lightweight.

1.3.7.1.2. Objective Tree:

Figure 5: Objective trees for the DDS waveform generator

1.3.7.1.3. Ranked Needs:

Easy to Use

Rich Frequency

Capability

Portable

Overall Score

Easy to Use

0

1

1

Rich Frequency Capability

1

1

2

Portable

0

0

0

Table 1: Pairwise Comparisons Matrix – General

Rationale: The rich frequency capabilities has priority since it was requested by the company sponsors

Store Predefined

Waveform Settings

SMA Output Ports

Overall Score

Store Predefined Waveform Settings

0

0

SMA Output Ports

1

1

Table 2: Pairwise Comparison – Ease of Use

Rationale: The upconverter used in ARTEMIS’s test setup all use SMA connections. The SMA ports connection is given priority so that conversion adapters are not needed.

Wide Range

Fine Resolution

Overall Score

Wide Range

0

0

Fine Resolution

1

1

Table 3: Pairwise Comparison – Frequency Capability

Rationale: Fine Resolution is give priority since small frequency resolution is need for their test setup.

Small

Lightweight

Overall Score

Small

0

0

Lightweight

1

1

Table 4: Pairwise Comparison – Portability

Rationale: The main object of this chart is to show that a lightweight device would be more desirable. Since this device will be moved around ARTEMIS, they requested the device be lightweight.

2. Requirements Specifications


2.1. The Requirements

Marketing Requirements

Engineering Requirements

Rationale

Have an easy to use interface

All output signals must be available on standard SMA female connectors

This allows the user to easily connect to the device, set and recall frequently used profiles

Four profiles will be available to set and select frequency configurations

The user must be able to interactively select a Frequency value and store this value into one of the user profiles

The device will provide a quick and simple means to select the frequency profile

Be small, portable and lightweight

The device will operate off a standard 120 volt AC wall outlet

Make the device portable and easier to move around

The generator should fit into a

4 inch x 12 inch x 12 inch volume

Have fine frequency resolution.

Be able to generate a wide range of output frequencies.

The output frequency must be able to reach all multiples of 100 Hz between 0 and 300 MHz.

This will allow ARTEMIS to test the upconverters more throe

The device must employ the DDS method of waveform

synthesis

Table 5: Marketing Requirements to Engineering Requirements Mapping

2.1.1. Engineering Requirements:

2.1.1.1. Engineering Requirement #: 1

(
1
)Engineering Requirement #:

The Requirement (list requirement below)

(
The

device

must

employ

the

DDS

method

of

waveform

synthesis
)

Requirement Type:

ideal constraint

non-verifiable

(
5
)Importance (1 = lowest, 5=highest):

(
2,

5
)Impacted Marketing requirements (list numbers):

Category (check all that apply):

adaptability functionality

availability health

budget (development) legal

documentation look and feel

economic (sales cost) maintainability

energy manufacturability

environmental (impact on) operational (constraint of

physical environment)

ergonomics other

ethical performance

political reliability safety social solution standards

sustainability/re-usability usability

Justification. Describe the rationale for this requirement. Why is this requirement needed? Why is it reasonable to expect it can be achieved?

(
This

requirement

was

specified

by

our

company

sponsor.
)

Testability/Verification. Describe the process your team will use to verify the requirement.

(
No

testing

is

required.

Either

we

will

have

employed

the

DDS

method

or

not.
)

History. If you change a requirement, indicate date of change, reason, and list the previous version of the requirement.

(
Requirment

established

on

10-23-2006.
)

2.1.1.2. Engineering Requirement #: 2

(
2
)Engineering Requirement #:

The Requirement (list requirement below)

(
All

output

signals

must

be

available

on

standard

SMA

female

connectors.
)

Requirement Type:

ideal constraint

non-verifiable

(
5
)Importance (1 = lowest, 5=highest):

(
3
)Impacted Marketing requirements (list numbers):

Category (check all that apply):

adaptability availability

budget (development) documentation economic (sales cost) energy

environmental (impact on)

ergonomics ethical

functionality health

legal

look and feel maintainability manufacturability operational (constraint of

physical environment)

other performance

political reliability safety social solution standards

sustainability/re-usability usability

Justification. Describe the rationale for this requirement. Why is this requirement needed? Why is it reasonable to expect it can be achieved?

(
The

usage

of

SMA

connectors

was

specified

by

the

company

sponsor.
)

Testability/Verification. Describe the process your team will use to verify the requirement.

(
Testing will be straightforward. It should be clear by inspection, whether SMA connectors are

used or not. However, the design will be connected to the corresponding connectors used by Artemis to

ensure

that

the

appropriate

connectors

were

chosen.
)

History. If you change a requirement, indicate date of change, reason, and list the previous version of the requirement.

(
Requirment

established

on

10-23-2006.
)

2.1.1.3. Engineering Requirement #: 3

(
3
)Engineering Requirement #:

The Requirement (list requirement below)

(
Four

profiles

will

be

available

to

set

and

select

frequency

configurations.
)

Requirement Type:

ideal constraint

non-verifiable

(
5
)Importance (1 = lowest, 5=highest):

(
6,4
)Impacted Marketing requirements (list numbers):

Category (check all that apply):

adaptability functionality

availability health

budget (development) legal

documentation look and feel

economic (sales cost) maintainability

energy manufacturability

environmental (impact on) operational (constraint of

physical environment)

ergonomics other

ethical performance

political reliability safety social solution standards

sustainability/re-usability usability

Justification. Describe the rationale for this requirement. Why is this requirement needed? Why is it reasonable to expect it can be achieved?

(
The

four

profiles

will

allow

the

user

to easily

switch

between

defined

frequencies.
)

Testability/Verification. Describe the process your team will use to verify the requirement.

(
Each

profile

will

be

tested

by

setting

frequencies

to

each

profile

and

check

its

frequency

using

a

spectrum

analyzer.
)

History. If you change a requirement, indicate date of change, reason, and list the previous version of the requirement.

(
Requirment

established

on

10-23-2006.
)

2.1.1.4. Engineering Requirement #: 4

(
4
)Engineering Requirement #:

The Requirement (list requirement below)

(
The

frequency

range

should

be

from

0

MHz

to

300

MHz
)

Requirement Type:
ideal

constraint

non-verifiable

(
4
)Importance (1 = lowest, 5=highest):

(
2
)Impacted Marketing requirements (list numbers):

Category (check all that apply):

adaptability functionality

availability health

budget (development) legal

documentation look and feel

economic (sales cost) maintainability

energy manufacturability

environmental (impact on) operational (constraint of

physical environment)

ergonomics other

ethical performance

political reliability safety social solution standards

sustainability/re-usability usability

Justification. Describe the rationale for this requirement. Why is this requirement needed? Why is it reasonable to expect it can be achieved?

(
ARTEMIS

needs

the

defined

frequency

range

requirement

for

their

upconverter

test

setup.
)

Testability/Verification. Describe the process your team will use to verify the requirement.

(
The

systems

frequency

output

will

be

hooked

up

to

an

oscilloscope

or

a

spectrum

analyzer.

The

generator

will

then

be

stepped

through

each

frequency

to verify

its

frequency

range.
)

History. If you change a requirement, indicate date of change, reason, and list the previous version of the requirement.

(
Requirement established on 10-23-2006. Requirement changed on 11-16-2006 the maximum frequency

was

mistakenly

typed

incorrectly.

Its

previous

max

frequency

was

400

MHz.

The

actual

max

frequency

is

300

MHz.
)

2.1.1.5. Engineering Requirement #: 5

(
5
)Engineering Requirement #:

The Requirement (list requirement below)

(
The

user

must

be

able

to

interactively

select

a

frequency

value

and

store

this

value

into

one

of

the

user profiles.
)

Requirement Type:
ideal

constraint

non-verifiable

(
4
)Importance (1 = lowest, 5=highest):

(
6,

4
)Impacted Marketing requirements (list numbers):

Category (check all that apply):

adaptability functionality

availability health

budget (development) legal

documentation look and feel

economic (sales cost) maintainability

energy manufacturability

environmental (impact on) operational (constraint of

physical environment)

ergonomics other

ethical performance

political reliability safety social solution standards

sustainability/re-usability usability

Justification. Describe the rationale for this requirement. Why is this requirement needed? Why is it reasonable to expect it can be achieved?

(
This feature will allow

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 40%)
:

• The chess game in Unity has made considerable progress, we are to the point where we can start developing variant support (using AI). We are continuing to set up the web application to embed the game in. Next week, we are hoping to make considerable progress with our support for chess variants.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Furthered development of chess game in Unity

• Continued developing the front-end interface for the web-application

• Researched algorithms suitable for variants.


Next week’s SMART goals:

• Finalize Chess application in Unity (Robert).

• Continue working on web-application (Michael).

• Develop AI algorithm and points-based system for variants (Izabella).

• Start updating our report to reflect our recent work (Ali).


Action Plan (task responsibility, timing, help needed):

• Finalize the chess game

• Continue front-end and back-end development for the web-application

• Develop point-based AI for variants and integrate it with already existing base game on Unity.

• Write our progress to our report


Open Issues, Risks, Change Requests:

• Finalizing our chess game

• Setup webGL with react

• Creating points-based AI system for variants


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application

2/6

2/13

3/8

Behind

schedule

Development has started in tandem with the chess application. We already a prototype, we will now begin iterating.

First Chess Game

2/6

2/20

3/8

Behind schedule

We are only missing a few pieces, currently movement and end condition checks

Electrical Engineering homework help

1. Laptop Computer System Research and Selection Presentation

Take a moment to review the details of this assignment below and gather any necessary files. Once you’re ready to submit your assignment, move on to Step 2.

Assessment Description

The purpose of this assignment is to use Microsoft Excel to create a laptop computer system cost comparison spreadsheet and utilize Microsoft PowerPoint to report the costs and pros and cons of various computer systems.

Your manager has approved the purchase of new laptop computers for your department.


Part 1 – Laptop Computer Cost Comparison

Create an Excel spreadsheet and, in a text box, identify and describe three software programs specific to your career field of study. This should not include Microsoft Office. The software should be used for productivity, data management, unique needs of the field, increasing market share, and increasing competitive advantage.

From this perspective, research various computer systems. In your Excel spreadsheet, identify and summarize the cost base for three laptop computer systems. Include information on the specifications listed below:

1. Computer brand and model

2. Price

3. CPU: type, clock speed, number of cores

4. RAM: amount and type

5. Screen size and resolution

6. Primary disk: capacity, hard drive or SSD

7. Optical disc drive (optional)

At the bottom of the spreadsheet, merge a block of several cells to create a large cell. In this area, provide a link to the website where this product can be found.

1. Add a new worksheet page and create two pie charts.

2. Pie Chart 1 should compare the cost of the three laptop systems.

3. Pie Chart 2 should compare the cost of the three software programs.

Only the Microsoft Excel spreadsheet file will be accepted. Do not submit any other file format, such as an Adobe PDF file, or you will not earn full credit.


Part II – Laptop Computer System Selection Presentation

Now that you researched three different laptop computer systems, select a laptop computer system that you chose to recommend to the management for the purchase. Create a PowerPoint presentation with a minimum of six slides that you can use to summarize and justify the laptop computer you have selected. Management has asked that you address the following in the presentation.

1. Computer brand and model

2. Price

3. CPU: type, clock speed, number of cores

4. RAM: amount and type

5. Screen size and resolution

6. Primary disk: capacity, hard drive or SSD

7. Optical disc drive (may be optional)

8. Detailed discussion of software specific to your career field of study that will be used for productivity, data management, unique needs of the field, increasing market share, and increasing competitive advantage (QuickBooks, SalesForce, Google Analytics, Epic, etc.), including the associated cost.

Only the Microsoft PowerPoint presentation file will be accepted. Do not submit any other file format, such as an Adobe PDF file, or you will not earn full credit.


General Requirements

Submit both the Excel spreadsheet file and the Microsoft PowerPoint presentation file. Do not submit any other file format, such as an Adobe PDF file, or you will not earn full credit.

Refer to the resource, “Creating Effective PowerPoint Presentations,” located in the Student Success Center, for additional guidance on completing this assignment in the appropriate style.

While APA style is not required for the body of this assignment, solid academic writing is expected, and documentation of sources should be presented using APA formatting guidelines, which can be found in the APA Style Guide, located in the Student Success Center.

This assignment uses a rubric. Please review the rubric prior to beginning the assignment to become familiar with the expectations for successful completion.

You are not required to submit this assignment to LopesWrite.

Rubric

Collapse All RubricCollapse All

collapse Excel – Three Laptop Computer Selection assessment

Excel – Three Laptop Computer Selection

15 points

Criteria Description

Excel – Three Laptop Computer Selection (Brand, Model, Price, CPU, RAM, Screen Size and Resolution, Primary Disk, Optical Disk (optional), Software, Cost Criteria)

5. Excellent

15 points

Details related to the laptop selected are complete and correct.

4. Good

12.75 points

Details related to the laptop selected are mostly complete and correct.

3. Satisfactory

11.25 points

Details related to the laptop selected are partially complete and correct.

2. Less Than Satisfactory

9.75 points

Details related to the laptop selected are incomplete or incorrect.

1. Unsatisfactory

0 points

Details related to the laptop selected are not included.

collapse Excel – Three Software Selections and Location (Should not include Microsoft Office) assessment

Excel – Three Software Selections and Location (Should not include Microsoft Office)

15 points

Criteria Description

Excel – Three Software Selections and Location (Should not include Microsoft Office)

5. Excellent

15 points

Three business-specific software selections for office productivity and tracking customer interactions, sales, and new leads are complete and meet the office productivity criteria.

4. Good

12.75 points

Three business-specific software selections for office productivity and tracking customer interactions, sales, and new leads are complete and meet most of the office productivity criteria.

3. Satisfactory

11.25 points

Three business-specific software selections for office productivity and tracking customer interactions, sales, and new leads are partially complete and meet some of the office productivity criteria.

2. Less Than Satisfactory

9.75 points

Three business-specific software selections for office productivity and tracking customer interactions, sales, and new leads are incomplete or incorrect.

1. Unsatisfactory

0 points

Business-specific software selections are not included.

collapse Excel – Two Pie Charts assessment

Excel – Two Pie Charts

15 points

Criteria Description

Excel – Two Pie Charts – One Comparing Three Laptop Systems and Another One Comparing Three Software Programs

5. Excellent

15 points

Charts are expertly crafted on the second worksheet.

4. Good

12.75 points

Charts are on the second worksheet and are complete and include relevant data, titles, and labels. Chart contains only minor errors.

3. Satisfactory

11.25 points

Charts are included in the second worksheet but lack relevant data from all required categories or contain errors in titling or labeling.

2. Less Than Satisfactory

9.75 points

Charts are on the second worksheet but are incomplete or incorrect.

1. Unsatisfactory

0 points

Chart are not present in the spreadsheet.

collapse Presentation of Content assessment

Presentation of Content

15 points

Criteria Description

Presentation of Content

5. Excellent

15 points

The content is written clearly and concisely. Ideas universally progress and relate to each other. The project includes motivating questions and advanced organizers. The project gives the audience a clear sense of the main idea. Persuasive, authoritative information from reliable, credible sources is included.

4. Good

12.75 points

The content is written with a logical progression of ideas and supporting information exhibiting a unity, coherence, and cohesiveness. Persuasive information is included from reliable sources.

3. Satisfactory

11.25 points

The presentation slides are generally competent, but ideas may show some inconsistency in organization or in their relationships to each other. Some persuasive information is included.

2. Less Than Satisfactory

9.75 points

The content is vague in conveying a point of view and does not create a strong sense of purpose. Some persuasive information from reliable sources is included. Some persuasive information is included but may be unreliable or lack credibility.

1. Unsatisfactory

0 points

The content lacks a clear point of view and logical sequence of information is unclear. Little or no persuasive information from reliable sources is included.

collapse Layout assessment

Layout

15 points

Criteria Description

Layout

5. Excellent

15 points

The layout is visually pleasing and contributes to the overall message with appropriate use of headings, subheadings, and white space. Text is appropriate in length for the target audience and to the point. The background and colors enhance the readability of the text.

4. Good

12.75 points

The layout background and text complement each other and enable the content to be easily read. The fonts are easy to read and point size varies appropriately for headings and text.

3. Satisfactory

11.25 points

The layout uses horizontal and vertical white space appropriately. Sometimes the fonts are easy to read, but in a few places the use of fonts, italics, bold, long paragraphs, color, or busy background detracts and does not enhance readability.

2. Less Than Satisfactory

9.75 points

The layout shows some structure but appears cluttered and busy or distracting with large gaps of white space or a distracting background. Overall readability is difficult due to lengthy paragraphs, too many different fonts, dark or busy background, overuse of bold, or lack of appropriate indentations of text.

1. Unsatisfactory

0 points

The layout is cluttered, confusing, and does not use spacing, headings, and subheadings to enhance the readability. The text is extremely difficult to read with long blocks of text, small point size for fonts, and inappropriate contrasting colors. Poor use of headings, subheadings, indentations, or bold formatting is evident.

collapse Speaker Notes assessment

Speaker Notes

15 points

Criteria Description

Speaker Notes

5. Excellent

15 points

Speaker notes are thorough and include substantial explanation and justification of computer system selections and relevant supporting details.

4. Good

12.75 points

Speaker notes are complete, justify computer system selections, and include explanation and relevant supporting details.

3. Satisfactory

11.25 points

Speaker notes are included but do not justify computer system selections or lack explanation and relevant supporting details.

2. Less Than Satisfactory

9.75 points

Speaker notes are incomplete or incorrect.

1. Unsatisfactory

0 points

Speaker notes are not included.

collapse Documentation of Sources assessment

Documentation of Sources

10 points

Criteria Description

Documentation of Sources (citations, footnotes, references, bibliography, etc., as appropriate to assignment and style)

5. Excellent

10 points

Sources are completely and correctly documented, as appropriate to assignment and style, and format is free of error.

4. Good

8.5 points

Sources are documented, as appropriate to assignment and style, and format is mostly correct.

3. Satisfactory

7.5 points

Sources are documented, as appropriate to assignment and style, although some formatting errors may be present.

2. Less Than Satisfactory

6.5 points

Documentation of sources is inconsistent or incorrect, as appropriate to assignment and style, with numerous formatting errors.

1. Unsatisfactory

0 points

Sources are not documented.

Electrical Engineering homework help

2021 Texas Power Outages:

Facts and Initial Thoughts

Hao Zhu

Assistant Professor

Department of ECE

The University of Texas at Austin

Acknowledgements: Dr. Ross Baldick, Power-Globe Discussions

February 22, 2021

Winter Storm 02/13-17

➢ Record long freezing temperature
and level of snowfall

➢ >4.5 million Texas homes and
business without power during the
peak outage time

➢ Water outages and quality issues

➢ Gas shortages and price spikes

➢ State of emergency declared

2

Outage map on 10-11am, 02/16
TexasTribune

Pre-storm timeline

➢ 02/08-02/11: ERCOT issued Notice, Advisory, and Watch for the expected
extreme cold weather on 02/11-02/16

➢ 02/11: ERCOT announced expecting record electric use due to extreme cold
weather; predicted peak demand at Monday (02/15) morning

▪ “Generators have been asked to take necessary steps to prepare their facilities for the
expected cold weather, which includes reviewing fuel supplies and planned outages and
implementing winter weatherization procedures.”

➢ 02/11: Electric utilities experienced local circuit outages

3

02/1402/08 02/10 02/11

Post-storm timeline

➢ 02/14: ERCOT requested energy conservation 02/14-02/16

6-7pm: set winter peak demand at 69,150 MW (summer peak 74,820 MW)

➢ 02/15: entered Energy Emergency Alert (EEA) at midnight (00:17)

01:25: EEA3, rotating outages, “10,500 MW load shed… Extreme weather
conditions caused many generating units – across fuel types – to trip offline and
become unavailable… ~34,000 MW of generation forced off the system”

➢ 02/18: majority of customers restored

➢ 02/19: ended emergency conditions

4

02/1902/14 02/15 02/18

5

➢ Why winter peak? Half

of Texas homes use

electricity for heating

➢ Projected peak of 75GW

in the morning of 02/15

➢ Actual demand 44 GW

due to controlled

outages

Viewing it as a car

➢ Peak demand = climb a hill

➢ Offline generation = two out of four tires

flat, or losing half of the horsepower

▪ 34 GW out of 75 GW

➢ We keep one backup tire that can

temporally relieve an emergency

➢ But unable to handle two flat tires

➢ Especially if the backup tire is also flat

6

Why generation offline?

➢ Generation plants not prepared for extreme cold

weather (lowest temp. below 0F)

➢ Gas supply (frozen pipelines and other priorities)

➢ Thermal (coal, gas) plants: 28GW ~37% capacity

▪ Nuclear: 1.3GW at South Texas Nuclear Power

➢ Renewable wind & solar: 18GW (26GW total)

▪ However, only 10GW in ERCOT winter peak planning

7

[Financial Times, NY Times]

http://www.ercot.com/content/wcm/lists/197391/ERCOT_Fact_Sheet_3.20.20.pdf

https://t.co/KNtbWIyzKz?amp=1

http://www.ercot.com/content/wcm/lists/197378/SARA-FinalWinter2020-2021.pdf

A closer look

➢ ~50% ERCOT capacity/
energy from natural gas

➢ ERCOT planned for 85GW
peak capacity in winter

▪ 87% thermal (~76GW)

▪ 9.7% wind (9.3GW)

▪ 1% solar (0.7GW)

➢ Expected low renewable
outputs and 100% thermal
availability in winter

8

Gas ↓ 15GW

Coal ↓ 3GW

Nuclear ↓ 1GW

Wind ↓ 4GW

9

https://www.eia.gov/beta/electricity/gridmonitor/dashboard/electric_overview/regional/REG-TEX

ERCOT to be blamed?

➢ ERCOT is a system operator: balance supply-
demand and control the flow of electricity

▪ Covers 90% of Texan electric load; 75% of land

▪ > 46,500 miles of transmission lines

➢ ERCOT doesn’t own the generation units

▪ Cannot mandate generation to weatherize

➢ Successfully handled the 69GW peak demand
on 02/14, no reported transmission issues

10

[Synthetic ERCOT grid, TAMU]

What about electricity market?

➢ Wholesale prices -> $9k/MWh (price cap)

▪ 300 times of the normal rate $30/MWh

➢ Scarcity market: aiming to incentivize generators
to self-invest in emergency mitigation solutions

➢ Some believe a capacity market is better, but
unlikely to cope with 1/3 loss

▪ back to the car example, it is like paying for some
generators to be the backup tire

➢ Market economics may fall short of
incentivizing long-term investment!

11

Hogan, William. “Electricity scarcity pricing

through operating reserves: An ERCOT window

of opportunity.” Harvard University. Cambridge

(MA) (2012).

www.spglobal.com

Interconnection is better?

12

➢ Many blame an independent Texas grid from
Texas pride & independence tradition in general

➢ ERCOT formed in 1970 as an ISO

▪ comply with NERC (NA Electric Reliability
Corp.) requirements

▪ not subject to FERC (fed energy regulator)

➢ Encourages efficiency/reliability, yet costly and
vulnerable to external failures (domino effects)

▪ 2003 US/Canada Northeast blackout

▪ 2011 Southwest blackout

https://www.texastribune.org/2011/02/08/texplainer-why-does-texas-have-its-own-power-grid/

13

Demand

exceeds

supply

Supply

maxed

out

~4-6GW

reserve

Demand

exceeds

supply

All our neighbors
(hit by same storm)
were almost maxed
out, if not under-
supply

[IEEE Smart Grid
Webinar, 02/19/21]

ERCOT is connected to East/Mexico

14

[ERCOT DC-Ties Operations, 2014]

➢ HVDC tie-lines ~1100MW

➢ Import (in neg. values) declined as our
neighbors maxed out

But wait, what about fed regulations?

➢ US Congress only authorized FERC to do annual
or seasonal assessments on generation adequacy.

▪ Like the ERCOT winter planning table earlier

➢ NERC requires N-1 reliability (losing one line/
unit), far from enough for this event

▪ ERCOT is actually better than N-1, capable to
cover the outages of 2 nuclear plants (~4GW)

➢ Each state regulator, public utility commission
(PUC) Texas in our case, determines other types
of generation adequacy assessments

15

[FERC Planning Resource Adequacy Assessment Reliability Standard, 02/18/21]

Looking back at 2011 Texas Blackout

➢ 02/02/2011, extreme cold led to a spike in electricity use, and coal/natural
gas plants and electric utilities couldn’t maintain service.

➢ Rolling blackouts across the state, from 20 minutes to over eight hours.

▪ “Generators were generally reactive as opposed to being proactive in their approach to
winterization and preparedness. The single largest problem during the cold weather event
was the freezing of instrumentation and equipment.”

▪ “Balancing authorities, Reliability Coordinators, Transmission Operators and Generation
Owner/Operators in ERCOT … should consider preparation for the winter season as
critical as preparation for the summer peak season.”

➢ Not aware of any states having this type of regulation

16

FERC/NERC “Outages and Curtailments During the Southwest Cold Weather Event of February 1–5, 2011

Why system-wide failure?

➢ Immediate cause is the extreme cold weather

➢ Fundamentally, power grids, like most other civilian infrastructure, are
designed to withstand random, local, small-scale failures

▪ cars, airplanes, buildings, transportation/water/gas networks

▪ based on cost-benefit analysis using a stochastic risk

➢ But overlooking factors of global impact can cause catastrophic outcomes

▪ Common-mode failures, or high-impact low-frequency (HILF) events

▪ Natural disasters: winter storms, hurricanes, earthquakes, solar storms, wildfires

▪ Malicious compromises: cyber attacks, EMP attacks

17

How to future proof?

➢ Enhancing resilience against extreme weather disasters

▪ we have witnessed more frequent occurrence of natural disasters

▪ proactively studying for these events, using more updated data/analysis

▪ designing systems with emergency controls in mind

▪ hardening the grid infrastructure (G/T/D) and across systems (gas/water)

➢ System-wide actions for ERCOT

▪ changing climate scenarios studies

▪ gas-electricity coupling

▪ weather-aware capacity model

▪ energy storage or flexible resources

18

Modernizing the local utility systems

➢ Sectionalizing circuits for flexible
network configuration

▪ Austin Energy had to put ALL non-
critical circuits without power for days

▪ Many commercial/residential users on
critical circuits (with government,
hospitals, ect.) were not impacted

▪ Could have implemented a rolling
blackout among all non-critical users

➢ Automatic load control, aka demand
response programs

19

[ucsusa]

Hao Zhu
haozhu@utexas.edu

http://sites.utexas.edu/haozhu/
@HaoZhu6

Thank you!

“It may appear that we are going in circles but,

at least, the circles are moving forward.”

– A PJM Committee Member

Indirectly from Ron Chu

Electrical Engineering homework help

Principles of Electrical Engineering II
332:222 Spring 2022

Project #1
Please submit to Canvas by Friday March 11, 2022 at 11:59PM.

Project format

For all the projects assigned in this course the following format is to be used

1. Each project is to have a title page, which will include your name at the top of the page as
well as your student ID number. The project number will be centered on the title page along
with the submission date. At the bottom of the title page please write “Principles of Electrical
Engineering II 332:222” and “Spring 2022”. The text on the title page shall be typed. The
page format should be based on 8.5″ x 11″ (American A sized) plain white paper for all the
pages in your report.

2. The title page will be followed by a brief introduction section, which will be one or two para –
graphs long. After the introduction section the various project tasks will be answered. Text
must be typed. Schematic diagrams and graphs will be drafted and plotted using a computer.
Mathematical formulas may be neatly printed in ink and then scanned or typed using a word
processor.

3. Class projects will be submitted to Canvas in PDF format. Please verify that your project
has been uploaded properly. Class projects should be your individual work only!

Project Description

This project is intended to introduce you to the concept of series resonance. This project
will help to prepare you for Lab Experiment #3 in the associated laboratory course. All the
mathematical tools that you need you have already learned in Principles of Electrical Engi-
neering I last semester. Please examine the schematic below.

This is a real circuit that I put together and performed measurements on. I used a function
generator (AC voltage source where the amplitude and frequency can be varied) to introduce
a fixed 2 volt peak sine wave to the circuit. This source was used as a reference voltage so it
will always have a phase angle of zero degrees associated with it. Then, using an oscillo-
scope (a test instrument which plots voltage versus time) I measured the resistor, capacitor,
and inductor voltages with their associated phase angles. See the four photos at the end of
this document. These values are recorded in the table below. To help improve the theoretical
results I measured all of the components using a good quality LCR meter. Note that I also
measured the internal resistance of the inductor so this should be taken into account in your
calculations.

TEST RESULTS

Freq (kHz) T (uS) |VR| (Volts) Angle VR
(Deg)

|VC| (Volts) Angle VC
(Deg)

|VL| (Volts) Angle VL
(Deg)

50 20 0.476 +72 3.38 -15 1.48 +160
70 14.3 1.22 +35 6.6 -57 5.6 +121

76.4 13.1 1.52 0 7.35 -89 7.1 +88
90 11.1 0.97 -46 3.88 -136 5.4 +39
100 10 0.7 -60 2.52 -151 4.2 +26

The theory behind this circuit is that the (complex) impedance of inductors ZL = j 2 π f L

and capacitors ZC = −
j

2 π f C
are both frequency dependent. Furthermore, the impedance

of these two components are in opposite directions on the complex plane. So, at one special

frequency, which is called the “resonant frequency” ω 0 or f 0 the reactive component of the
circuit impedance from the inductor will cancel out the reactive component of the circuit im –
pedance from the capacitor and the total impedance of the circuit will be purely resistive. At
the resonance frequency, the current in this series circuit will be at a maximum and the phase
angle between the source voltage and the circuit current will be zero. The voltage across the
resistor will also be at a maximum because vR = i×R and R has an angle of zero degrees
associated with it.

Task #1 10 pts

Starting with |XL|=|XC| derive the formula for the resonant frequency f 0 (you have

seen this many times before as ω 0 = 2 π f 0 =
1

√LC
).

Task #2 30 pts

Find the formulas for ztotal(f), vR(f), vC(f), vL(f), and i(f) (note that these are complex quanti-
ties that are a function of frequency – remember phasors from PEE1) in the series RLC circuit
above. Enter the real component values into these formulas (don’t forget the inductor resis –
tance) so the only variable in your formulas will be the frequency f and everything else will be
a constant.

Task #3 50 pts

Calculate the theoretical values of VR, VC, and VL (both magnitude and phase angle) at the
test frequencies used in the table above. That is 50kHz, 70kHz, 76.4kHz, 90kHz, and
100kHz. Create a table for these calculated values, in the same order as in the table above,
so they can be easily compared to the experimental results. Include this table in your report.

Hint: You can use an equation solver or programming language, that can handle complex
numbers, for your calculations. It is a lot faster then doing your calculations using a scientific
calculator. I used the MATLAB programming language to do my calculations for this project.

Question: Can the voltage magnitude at resonance, across any of the circuit components, be
greater than the magnitude of the source voltage? 10 pts

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 0%)
:

• We have begun to investigate technologies for our application. We have also completed a low-level design for the project. Our basic idea is creating a chess variant game via a 3d game development engine, and then utilizing a web application architecture to host that game.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Investigated Stockfish as an avenue for creating this project. Forking this package and editing it is an avenue but not the best way to go about this

• Investigating a game development engine (Unity) for creating the base chess game.

• Learning languages for this project (C#, JavaScript, Python)


Next week’s SMART goals:

• Create a GitHub Repository for team members (potentially two, one for the chess game and one for the web-app) (Michael, Robert)

• Learn more about game development with Unity and C# (Michael, Ali, Izabella)

• Discovery on Web application architecture (All)

• Begin writing Chess application in Unity (Robert).

• Begin design our UI for the website (Izabella, Ali)


Action Plan (task responsibility, timing, help needed):

• Learn more about the languages and technologies we are going to be using and how they will fit together

• Get a base setup for the web application and chess game on GitHub

• Start Design chess game UML diagram

• Start creating the base chess game

• Set up bi-weekly/weekly meeting time with advisor


Open Issues, Risks, Change Requests:

• Finalizing choices of technologies/frameworks that will be used in project


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application UI design

1/30

1/30

N/A

On schedule

First prototype of web application server

2/6

2/6

N/A

On schedule

First Chess Game

2/6

2/6

N/A

On schedule

* Examples adapted from CREG 257/258 at Lehigh University

Electrical Engineering homework help

Mid Exam Project

DDL: Mar/24/2022 23:59

Please write a paper to discuss the Texas power outage during the 2021 Feb winter storm.
You can pick up any topic which is closely related to the Texas power outage. The core topic
must be in the electric power industry.

Evaluate Standards.

1. The number of pages is within 3 – 4 pages. The font of the paper is 12 in Times
New Roman, single line space. (10 points)
2. Please explain what happened during the Texas power outage. You can pick up
one angle to do an analysis. For example, water outage in Houston area; rolling power
outage in Austin/ Houston/Dallas; Solid numerical data must be provided and the
references for these data must be provided. (30 points)
3. Please explain why it happened. For example, in order to balance the demand
and supply, the rolling power outage strategy is deployed which can save the frequency
of the Texas electricity grid. (30 points)
4. Please provide suggestions to reduce the impact of the power outage and the
probability of the power outage. (30 points)

Electrical Engineering homework help

Title

Table of Contents

List of Figures 2
Executive Summary 3
Problem Statement 4
Need 4
Objective 4
Background and Technology Survey 5
Requirements 6
Marketing Requirements 6
Engineering Requirements 6
Constraints and Tradeoffs 7
Applicable Standards 8
House of Quality 9
Design Phase 9
Ethical and Societal Considerations 10
Initial Hypothesis & BMC Model 10
Project Management Plan 13
Conclusion 14
Appendix 15
References 15
Interviews 16
Team Member Resumes 19

(
12
)

List of Figures

House of Quality Matrix 9
Phases of Design 9
BMC Model 1 11
BMC Model 2 12
Gantt Chart Part 1 13
Gantt Chart Part 2 14


Executive Summary

The goal of this project is to develop a Chess Variant Application that provides a variety of unique gameplay twists on the classic game of chess. This application will give players the ability to play any variants of chess against AI agents or other humans online. There are not many applications that offer a unique spin on the gameplay of chess like variants. There is also not one localized application where players can play with others online and AI agents. This provides our project a good opportunity in the market.

We will be able to utilize many open-source technologies for this application. For example, we can utilize already existing AI agents for chess, and build upon them to work for variants of chess. We can also do this for the main chess game itself. Utilizing an open source technology and editing to fit our specific needs within a variant of chess. There are also many additional features that we can add to enhance the user experience of the application.

In order for us to determine and narrow down what exactly would be the most useful integrations for our device, we will conduct customer interviews with Dr. Christopher Flora, an avid chess enthusiast, and Dominic Matessyk, a chess game and chess AI developer.


Problem Statement


Need

A Chess Variant Application will allow many chess game players to experience chess in a way they have never before. It will also allow for players to learn and improve on their skills in chess or a chess variant. Currently, there exist few applications where users are able to play chess variants against another human or an Artificial Intelligent (AI) agent. For example, there is Chess.com, a website where players can play against other humans online, and ChessV, a desktop application that allows the player to oppose an AI agent for a select amount of chess variants. Multiplayer opponents and AI agent opponents exist on different platforms.

For our application, we will mainly be focusing on the amount of variants able to be played, and the AI that the player will be able to oppose. There will also be a strong focus on online multiplayer with the application.


Objective

The objective of our Chess Variant Application is to provide chess players with an accessible and safe platform to experience chess variants on. We also want to provide a customizable AI agent to allow players to play against any difficulty of the agent instead of preset values. This will allow for players to learn any level. Potentially there could be a feature that predicts what AI agent level will line up with the current players playstyle.

With this application we also hope to provide a satisfactory and safe online experience with other players from a cybersecurity, and social perspective. For example, we do not want to share any personal information of one player with another player. Or if there is an online chat feature, we would like to have this automatically moderated as a safe chat for all players.

Lastly, we hope to provide a robust and computationally efficient AI agent or Machine Learning model that is comparable, if not better, than other chess game variants on the market.

Background & Literature Survey

Chess is a board game in which two players compete against each other. It is among the most popular games globally, with millions of players. Playing chess results in better brain function, enhanced memory, and improved attention (Zhang, Li, and Xiong, 2019). Various platforms enable people to play chess online; (Nair, Marathe, and Pansambal, 2018.) this includes chess.com, Red hot pawn, Liches, and Chess24.

These platforms have varying features and functionality to enable people, learn, play and contest efficiently and with less complexity in using the site.

Chess.com, the most popular site, enables an individual to sign up and play against the computer or a human competitor. Its standard features include unlimited chess games in different styles and variants, supporting clubs and leagues with an unlockable achievement system.

Red hot pawn is a one-of-a-kind gameplay experience, particularly for those who favor a slower pace. It has a user-friendly platform that enables juggling numerous games a breeze. In addition, there is an educational forum and a unique support structure. While there are no prerequisites for using Lichess, it does provide the ability to learn and play chess. It comes in various flavors, including cloud-based chess courses, and it supports a wide variety of languages.

These sites are significant since they are free to get and can play chess variants against a human or an AI rival (Wilkenfeld, 2019).

Chess has gone a long way since it first appeared on a computer, and each year, a new chess engine emerges that outperforms the preceding one. Each engine has been improved, and new techniques to manipulate the graphical user interface have been devised (LinLin, YuNu, YaJie, and Guoqiang, 2017). A site that provides a changeable Artificial Intelligence agent that has the potential to allow gamers to play against the agent’s complexity instead of preset levels are desired. This will allow players to learn at their own pace (Su, Shiau, Guo, and Shiau, 2009). A

component that forecasts which Artificial Intelligence agent rank would align with the actual player’s playstyle could be included.


Requirements


Marketing Requirements

We found several requirements customers have for a software application. The first is that the application should be low cost to make it more accessible. The second requirement is that the software should be easy to use. While a slight learning curve is inevitable, if an application is too much of a hassle to use, customers will opt for alternatives. The third requirement is that updates are quick. This is especially important if there are bugs that make the application unenjoyable to use. The fourth requirement is that it has a variety of uses, this attracts a large user base. The fifth requirement is that it is compatible with multiple platforms. In a world where not everybody uses

the same operating system, this is essential to reach as many people as possible. The sixth requirement is that the interface is modern-looking. Unattractive UI can repel users. The seventh requirement is that the application is not resource-intensive. Not all customers will have the same level of power in the systems they are using, so we need to be mindful of that. The eighth requirement is that customer support resources are available, so that they can reach the developers in case of any issues. The ninth requirement is that the app is engaging. As a game application, it is not useful if it isn’t fun to the customers. Lastly, it should run reasonably fast.


Engineering Requirements

There are several engineering requirements for our project. Firstly, that our code is clean. Messy code will inhibit our process of designing (and any future updates). Secondly, we need to compare it to similar applications and make ours a top performer. The third engineering requirement is speed, not only is excessively slow software bad for customers but it also makes it more difficult for us to test. The fourth requirement is innovation. The fifth requirement is good documentation, this is necessary if our software becomes open-source, and it also serves to help

us as developers. The sixth requirement is not a lot of bugs, we need to minimize bugs as much as possible in our process. The seventh requirement is secure, security is very important so that our content and data is not compromised. Additionally, our software should be scalable. Given that there are many possible variants and features for the application, it is important that the app could grow instead of staying stagnant. Lastly, our application needs to be both cost efficient and efficient to maintain.


Constraints and Tradeoffs

Our application has a number of constraints and tradeoffs that factor into the design and decisions that must be made. Four main constraints and tradeoffs that must be considered for our application are: which platform it will be released on, whether it will have 2D or 3D graphics, the chess variants that will be implemented in it, and time.

The platform we choose for release will affect the processing power we have available at our disposal and what types of input systems we must design for. We will also have to consider the cost to publish on each of these platforms. Publishing on multiple platforms will expand the reach we have to our audience but also increase the complexity of the project as we will have to design ways for the user to interface through each one. Due to the different processing power available to each platform and user devices, platform selection may also impact graphical decisions if we aim to ship to lower-end devices.

A choice will also have to be made between 2D or 3D graphics. 3D graphics can look more appealing and realistic and set our app apart aesthetically, but it also introduces complexity into the system. The 3D perspective could lead to a more complicated user interface if camera controls are taken into consideration and the less symbolic representation of 3D could obscure gameplay concepts compared to a simpler 2D application. A 2D representation could remove the need for any sort of camera control and provide a clear symbolic representation of gameplay concepts.

The types and number of variants we will implement in our application also comes with a handful of tradeoffs. We can only implement a finite number of chess variations and each one will add to the scope of the project. Some variations may be more complicated than others, calling for different board shapes or more complex piece interactions. It is important to not scope

too big but we must also consider that the variants we present our one of the biggest features that will set our application apart from others. Because it will be necessary to implement a variety of chess variants, the design of our underlying chess system must be very flexible to host a variety of altered rulesets, boards, and pieces. The variants we implement will also play a large role in the complexity of training an AI system to play the different variants we implement.

The last and tightest constraint on this project is time. The project will have a finite time to be completed in the spring semester. It is important to scope the project so that it can be completed within this time frame. Our team will have to define and split up the feature set of our application into a variety of tasks to deliver a quality product in a timely manner.


Applicable Standards

Our application will have to adhere to the standards of the platforms it is published on. It may be necessary to develop publicly available privacy policy or terms of service documents.

This application will also have to disclose any sensitive permissions it may need on some platforms such as mobile storage. It will also be important to adhere to any family or content rating policies a platform may have (such as Android’s Designed for Families policy) when deciding on target audiences, the nature of advertisements, monetization, and online interactions we may put within the application.


House of Quality


Design Phase

We are currently in the “Concept Generation” phase of design. We have identified the

problem (the scarcity of cross-platform applications featuring chess variants). We have also researched existing chess AI frameworks and applications. We developed both engineering and marketing requirements (discussed more in depth in the Requirements section).


Ethical and Societal Considerations

As with any software application, we must be diligent to respect customers’ preferences as to how their data would be used. We would obtain explicit consent to use data, and not sell it to any company. In addition, if there is the option for users to contact each other, we would need safeguards against online harassment and bullying. We would need to practice good security, so user information is not leaked to third parties.


Initial Hypothesis & BMC Model

Initial

Hypothesis: Customers will buy our product because there is a large demand for innovative multiplayer games that utilize artificial intelligence.

After 1st Interview

Hypothesis: Customers will buy our product because we will offer popular chess variants to players on multiple accessible platforms.

After 2nd Interview

Hypothesis: Customers will want to buy our product because there is a demand for innovative chess software, specifically ones with twists on gameplay and features to help users hone their skills.

BMC Model:


Project Management Plan


Conclusion

Our goals for Senior Design one were to form a team, select a topic, and find an advisor. We achieved all three of these things, although we are still formulating all of the details for our project. In the future, we will design and implement our software.

Appendix A (References)

Need at least 5 references, in IEEE/ACM format

LinLin, W., YuNu, W., YaJie, W., and Guoqiang, C. 2017. Research on the Surakarta chess game program based on unity 3D, 2017 29th Chinese Control and Decision Conference (CCDC),7671-7674, Doi: 10.1109/CCDC.2017.7978580.

Nair, A., Marathe, K., & Pansambal, S. 2018. Literature Survey of Chess Engines. International journal of engineering research and technology, 5.

Su, K., Shiau, S., Guo, J., and Shiau, C., 2009. Mobile Robot Based Online Chinese Chess Game, 2009 Fourth International Conference on Innovative Computing, Information and Control (ICICIC), 528-531, Doi: 10.1109/ICICIC.2009.261.

Wilkenfeld, Y. 2019. Can Chess Survive Artificial Intelligence? The New Atlantis, 58, 37–45.
https://www.jstor.org/stable/26609113

Zhang, Y., Li, S, and Xiong, X 2019. A Study on the Game System of Dots and Boxes Based on Reinforcement Learning, 2019 Chinese Control and Decision Conference (CCDC), 6319-6322, Doi: 10.1109/CCDC.2019.8833043.

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 5%)
:

• After meeting with our Advisor, we have decided to change focus a little this week. We have decided to go full force on developing the game itself. All members have been working hard on learning and building Chess in Unity. A small amount of progress has been made on the web application, however, we have decided that we may want to wait to design the website until we have a working copy of the chess game to place there. With help from our advisor, we have found a few Chess AI engines and plan to use Stockfish. We are creating a GUI that communicates with Stockfish using the UCI protocol.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Learned more about Unity as well as well as continued to make chess game

• Investigated webgl for reactjs

• All members setup the code for our chess repo

• Investigated Stockfish and other chess engines

• Learning languages for this project (C#, Unity, JavaScript)


Next week’s SMART goals:

• Setup WebGL and other packages (webpack, babel… etc) on the web application. (Michael)

• Learn more about game development with Unity and C# (Michael, Ali, Izabella)

• Continue writing Chess application in Unity (Robert, Izabella, Michael, Ali).

• Continue researching stockfish and other chess engines for our game (Izabella).

• Begin design our UI for the website and assets (Izabella, Ali)


Action Plan (task responsibility, timing, help needed):

• Learn more about Unity and chess game development
• Learn more about Stockfish and other Chess Engines

• Start Design chess game UML diagram

• Continue creating the base chess game

• Get the web application ready to receive and host the chess game


Open Issues, Risks, Change Requests:

• Finalizing choices of technologies/frameworks that will be used in project


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application

2/6

2/13

2/27

Off schedule

We need the first prototype of the chess game to have this prototype

First Chess Game

2/6

2/20

N/A

On schedule

Design graph of Architecture

2/6?

2/6

N/A

On schedule

We have a small design already made, and need to extrapolate


Deliverables:

Figure 1: Level 0/1 Design of Architecture

* Examples adapted from CREG 257/258 at Lehigh University

Electrical Engineering homework help

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
80%

82%

84%

86%

88%

90%

92%

94%

D001

Vin = 48 V @ 400 kHz
Vin = 48 V @ 600 kHz
Vin = 48 V @ 800 kHz
Vin = 48 V @ 1 MHz

Q1

Vin C1

LMG5200

Q2

* *

C2

T1

ISO7420 TPS53632

UCC27512

VFB

Q3

Q4

L2

L1

CO RL

SGND

Vout0.8 V ~ 1.2 V / 40 A

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

TI Designs
LMG5200: 48 to 1 V or 40 A Single-Stage Converter
Reference Design

All trademarks are the property of their respective owners.

Description
The PMP4497 is a gallium nitride (GaN) based
solution for 1.0-V and 40-A core, field programmable
array (FPGA), and application specific integrated
circuit (ASIC) applications. With high integration and
low switching loss, the GaN module LMG5200 enables
a high-efficiency, single stage from the 48 to 1.0 V
solution to replace the traditional two-stage solution.
This design shows the GaN performance and the
system advantages compared with the 2-stages
solution. A low-cost ER18 planar printed circuit board
(PCB) transformer is embedded on the board. The
design was achieved in a compact form factor (45 mm
× 26 mm × 11 mm). The size could be further reduced
by optimizing frequency and components. A design
guide with complete test data is provided to facilitate
new designs.

Resources

PMP4497 Design Folder
LMG5200 Product Folder
TPS53632 Product Folder
ISO7420FE Product Folder
UCC27512DRSR Product Folder
TLV70450DBVR Product Folder
TLV70433DBVR Product Folder
PMP4435 Tools Folder

ASK Our E2E Experts

Features
• Input Voltage From 36 to 60 V
• Single Stage Half-Bridge and Current Doubler
• Peak Efficiency up to 93.7% at 48 V, 1.0 V, and

600 kHz
• LMG5200 GaN FET Module
• DCAP+ Control With the TPS53632
• 400-kHz to 1-MHz Operation Frequency
• I²C Configurable From 0.8 to 1.2 V
• Optional Resistor-Configurable Load-Line
• Output Over Voltage Protection (OVP), Overcurrent

Protection (OCP), and Output Under Voltage
Protection (UVP)

Applications
• Servers and High-Performance Computing
• Telecom DC-DC Module
• Industrial Board Computer, Field Programmable

Gate Array (FPGA), and Application Specific
Integrated Circuit (ASIC)

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.

System Overview www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

1 System Overview

1.1 System Description
The PMP4497 implements the 48- to 1-V single-stage power conversion using a hard-switching half-
bridge converter with the current-doubler synchronize rectifier. Figure 1 shows the topology implemented
in this board. A LMG5200 and EPC2023 GaN FETs are used on the primary side and secondary side
respectively. With the GaN MOSFET advantages, such as the zero-reverse recovery, low capacitance,
and low Rds-on, the converter could achieve a smaller size and a higher efficiency compared with a
traditional two-stage solution (for example, an eighth brick and the 12-V POL module).

Because the half-bridge converter is transformer-based, the converter can be isolated. The TPS53632
controller can support an isolated converter by using a digital isolator, for example, the ISO7420, to drive
the primary-side LMG5200. The PMP4497 supports input voltage from 36 to 60 V and output voltage from
0.8 to 1.2 V; the default output voltage is 1.0 V. The output current supports up to 40 A; fan cooling is
recommended to help dissipate the heat when operating above 20 A. The output voltage is programmable
through an I²C interface. See the TPS53632 data sheet (SLUSBW8) for the details of the I²C program
command and the data format.

1.2 Key System Specifications

Table 1. Key System Specifications

PARAMETER TEST CONDITIONS MINIMUM TYP MAXIMUM UNIT
INPUT AND OUTPUT CHARACTERISTICS

Input voltage
range 36 48 60 V

Input current VIN= 36 V, VOUT= 1.2 V, IOUT= 40 A — — 1.4 A
Output voltage I²C programmable 0.8 1.0 1.2 V
Output voltage

tolerance IOUT= 0A — — 10 mV

Output current — — — 40 A
Over-current

protection — — 60 A

SYSTEM CHARACTERISTICS
Switching
frequency 400 600 1000 kHz

Peak efficiency VIN= 48 V, VOUT= 1.0 V, IOUT= 15 A, @600kHz withoutcontroller and driver losses — 92.9 — %

Full-load
efficiency

VIN= 48 V, VOUT= 1.0 V, IOUT= 40 A, at 600kHz without
controller and driver losses — 89.9 — %

Transient load
voltage variation

Transient at the 25% full load (10 A), the ELoad slew
rate is 2.5 A/µs — ±3 — %

6

4

LMG45200

UVLO

UVLO and
Clamp

Level
Shifter

5

8

3

1

2

9

7

VCC

HI

LI

HB

VIN

HS

SW

PGND

AGND

Copyright © 2016, Texas Instruments Incorporated

Q1

Vin C1

LMG5200

Q2

* *

C2

T1

ISO7420 TPS53632

UCC27512

VFB

Q3

Q4

L2

L1

CO RL

SGND

Vout0.8 V ~ 1.2 V / 40 A

Copyright © 2016, Texas Instruments Incorporated

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

1.3 Block Diagram

Figure 1. PMP4497 Block Diagram

1.4 Highlighted Products

1.4.1 LMG5200
The LMG5200 device integrates an enhancement-mode GaN FET half-bridge power stage with a 100-V
driver, which provides a compact solution.

The device extends the advantages of discrete GaN FETs by offering a more user-friendly interface. The
device is an ideal solution for the applications requiring high-frequency and high-efficiency operation in a
small form factor. Integration reduces the board clearance and creepage needed for a discrete solution
while minimizing the loop inductances to ensure fast switching and low ringing.

Figure 2. LMG5200 Functional Block Diagram

ADDR

OSR/USR

USR

OSR

ISUM

DROOP

Copyright © 2016, Texas Instruments Incorporated

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

1.4.2 TPS53632
The TPS53632 device is a driverless step-down controller with I²C control. Its advanced features, such as
D-CAP+ architecture, provide fast transient response, and high-efficiency operation with minimized output
capacitance. The TPS53632 device supports the standard I²C revision 3.0 interface for dynamic control of
the output voltage and current monitor telemetry. The device also has dynamic phase adding and
shedding control and is able to enter single-phase, discontinuous-current mode operation to maximize
light-load efficiency.

Figure 3. TPS53632 Functional Block Diagram

1.4.3 ISO7420
The ISO7420 is a low-power, dual-channel digital isolator. The device is used in the design to deliver
isolated control signals from the secondary side to the LMG5200 on the primary side. The ISO7420
provides galvanic isolation up to 2500 V RMS for 1 minute per UL and 4242 VPK per VDE. This device
has two isolated channels. Each channel has a logic input and output buffer separated by an insulation
barrier. Used in conjunction with an isolated power supply, the device prevents noise current from entering
the local ground and interfering with or damaging sensitive circuitry.

1

2

3

4

5

6

VDD

200 N��

230 N��

UVLO

VDD

VDD

Copyright © 2016, Texas Instruments Incorporated

1

2

3

4

8

7

6

5

VCC1

INA

INB

GND1

VCC2

OUTA

OUTB

GND2

Is
o

la
tio

n

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 4. ISO7420 Block Diagram

1.4.4 UCC27512
The UCC27512 is a single-channel, high speed, low-side gate-driver device. The device can effectively
drive the MOSFET and insulated gate bipolar translator (IGBT) power switches with 4-A peak source and
8-A peak sink asymmetrical drive capability. Using TI intellectual property (IP) that inherently minimizes
shoot-through current, the UCC27512 is capable of sourcing and sinking high peak-current pulses into
capacitive loads and offering rail-to-rail drive capability with small propagation delay, typically 13 ns. In the
PMP4497 design, a duty signal to IN- of the driver to drive the synchronous rectifier MOSFET. IN+ is
bypassed by connecting it to VDD directly.

Figure 5. UCC27512 Block Diagram

t0 t1 t2 t3 t4 t5

t

t

t

t

t

Vgs_Q1

Vgs_Q2

t

iL1

iL2

iO

Io/2

VNP_T1

Io/2

Io

+Vin/2

-Vin/2

TSTS/2

System Design Theory www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

2 System Design Theory
Benefitting from the output ripple current cancellation technique, a half-bridge converter with a current
doubler rectifier circuit is suitable for low-profile, high-voltage input and large output current applications
and provides higher efficiency. The converter key theoretical waveforms are shown in Figure 6.

Figure 6. Half-Bridge with Current Doubler Timing Diagram

* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t3 ~ t4

SGND

Copyright © 2016, Texas Instruments Incorporated

* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t2 ~ t3

SGND

Copyright © 2016, Texas Instruments Incorporated

* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t1 ~ t2

SGND

Copyright © 2016, Texas Instruments Incorporated

* *

C2

C1

CO RL

T1

Q1

Q2

Q3

Q4

PGND

LMG5200

L1

L2

Vin Vout

t0 ~ t1

SGND

Copyright © 2016, Texas Instruments Incorporated

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

2.1 Operation Modes of the Converter With Current Flow
The converter in the continuous current mode (CCM) mode has four operation modes during one full
switching period as shown in Figure 7.

Figure 7. Operation Modes With Current Flow

O S

in P

V N
M D

V 2 N
= = ´

´

( )0 S 0 S
Vin NS

V D T V 1 D T
2 NP

æ ö
´ – ´ ´ = ´ – ´ç ÷

è ø

( )0 S
1

1

V 1 D T
i

L

´ – ´
D =

( )00 V-

Sin
0

P

NV
V

2 N

æ ö
´ -ç ÷

è ø

2
0 2

di
0 V L

dt
– = ´

1
0 1

di
0 V L

dt
– = ´

Sin 2
0 2

P

NV di
V L

2 N dt
´ – = ´

1
0 1

di
0 V L

dt
– = ´

2
0 2

di
0 V L

dt
– = ´

1
0 1

di
0 V L

dt
– = ´

2
0 2

di
0 V L

dt
– = ´

Sin 1
O 1

P

NV di
V L

2 N dt
´ – = ´

System Design Theory www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

2.2 Circuit Operation and Description
Time interval t0 → t1:
During the t0 → t1, Q1 and Q4 are on, and Q2 and Q3 are off. The transformer T1 secondary winding begins
to charge the output inductor L1, and the L2 is discharged to the output capacitor and the load.

Time interval t1 →t2:
During the t1 → t2, Q1 and Q2 are off, and Q3 and Q4 are on. Both L1 and L2 discharges the current to the
output; the inductor current is discharged linearly.

Time interval t2 →t3:
During the t2 → t3, Q1 and Q4 are off, and Q2 and Q3 are on. The transformer T1 secondary winding
inverses the polarity and begins to charge the output inductor L2, and the current in L1 is discharged to the
output capacitor and the load.

Time interval t3 →t4:
During the t3 → t4, Q1 and Q2 are off, and Q3 and Q4 are on. Both the L1 and L2 are discharged to the
output; the inductor current is decreased linearly.

According to the simplified operation models, during the t0 → t1 (DTs) the winding begins to charge the

inductor L1 with the voltage , and the current i1 increases linearly. Within the t1 → t4 (1-D), the
current i1 decreases with the voltage . The inductors ripple current is as follows:

Based on the voltage-second balance of the inductor, the CCM voltage transfer ratio is

www.ti.com Getting Started Hardware

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

3 Getting Started Hardware

3.1 Hardware
The converter output range is from 0.8 to 1.2 V, and the input voltage range is from 36 to 60 V. Operation
should be within the input/output voltage ranges.

If the converter shuts off due to UVP or OCP, the controller IC must be rested to re-enable the converter.
To change the output voltage, the I²C bus should be used to set the TPS53632. Consult the user guide for
the TPS53632 for the necessary VID protocol (SNVU520). The TPS53632 controller’s switching
frequency, voltage ramp rate, load line, and OCP could be changed by modifying resistor values on the
board. The TPS53632 data sheet (SLUSCJ3) includes the detailed procedures to choose these
components.

3.1.1 Test Equipment
• DC voltage source: supplies the EVM from 36 V to 60 V, output current >2A
• DC bias source: 6 to approximately 9V or 0.5 A, two outputs for the primary and secondary
• Oscilloscope: >200-MHz operation, use oscilloscope probes with a pigtail spring ground clip instead of

the standard alligator clip
• DC multimeter: capable of 100-V measurement, suitable for efficiency
• DC load: supports 1-V operation at up to 50 A in current-mode operation
• Fan cooling: 200-LFM minimum airflow is recommended to cool the PCB when operating over 20-A

output current

3.1.2 Measurement Procedure
The following procedure is used to measure the board.
1. Connect the input and output supplies as shown in Figure 8.
2. Connect the oscilloscope to the board to measure input/output voltage. Use a bayonet nut connector

(BNC) to a subminiature version A (SMA) cable or differential probe for the noise immunity.
3. Connect the bias supply. The onboard LDO provides 5 and 3.3 V to the power and control circuitry.
4. Power up the input supply. Operation below 36 V may result in the output voltage range out of

regulation.
5. Power up the bias supply to start the converter. The output voltage will ramp up and the output voltage

should be in regulation.
6. Enable the electronic load and set to a desired load current.
7. Test and measure the input/output voltage response, efficiency, and so forth.

3.1.3 Shutdown Procedure
After the measurements have been completed, shut down the board by the following steps:
1. Disable the input voltage supply.
2. Disable the electronic load.
3. Disable the bias supply.

Testing and Results www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4 Testing and Results

4.1 Test Setup

Figure 8. Connection Points

Figure 9. Testing Setup With Full Load

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 10. Oscilloscope Probe Connections

Input Voltage (V)

P
o
w

e
r

L
o
ss

(
W

)

34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

D003

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
84%

86%

88%

90%

92%

94%

D002

Vin = 36 V
Vin = 48 V
Vin = 60 V

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
80%

82%

84%

86%

88%

90%

92%

94%

D001

Vin = 48 V @ 400 kHz
Vin = 48 V @ 600 kHz
Vin = 48 V @ 800 kHz
Vin = 48 V @ 1 MHz

Testing and Results www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2 Test Data
The following sections detail the typical performance curves and waveforms of the PMP4497.

4.2.1 Efficiency
Note that most of the efficiency results in this section do not include the controller losses (aside from
Figure 14). The default output voltage is 1.0 V.

Figure 11. Efficiency Curve Without Controller Loss Versus Switching Frequency

Figure 12. Efficiency Curve Without Controller Loss Versus Output Current

Figure 13. Power Loss (No Load) Versus Input Voltage

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
80%

82%

84%

86%

88%

90%

92%

94%

D005

Vin = 48 V @ 0.8 V 600 kHz
Vin = 48 V @ 1.0 V 600 kHz
Vin = 48 V @ 1.2 V 600 kHz

Output Current (A)

E
ff

ic
ie

n
cy

0 5 10 15 20 25 30 35 40 45
78%

80%

82%

84%

86%

88%

90%

92%

D004

Vin = 36 V
Vin = 48 V
Vin = 60 V

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 14. Efficiency Curve with Controller Loss Versus Output Current

Figure 15. Efficiency Curve without Controller Loss Versus Vout Change (Through I²C)

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2.2 Transient Load Waveforms

Transient load (0 to 25%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (25 to 50%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (50 to 75%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (75 to 100%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (10 to 90%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

Transient load (0 to 100%)
C1: 48-V input voltage 10.0 V/Div
C2: 1.0-V output voltage 20.0 mV/Div

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2.3 Switching Node Waveforms (Full Bandwidth)

Primary Vsw versus PWM1_P no load
C1: Vsw switching node 10 V/Div
C2: PWM1_P driver signal 2.0 V/Div

Primary Vsw versus PWM1_P full load
C1: Vsw switching node 10 V/Div
C2: PWM1_P driver signal 2.0 V/Div

Primary Vsw versus PWM1_P full load
C1: Vsw switching node 20 V/Div
C2: PWM1_P driver signal 5.0 V/Div

Primary Vsw versus PWM1_P full load
C1: Vsw switching node 20 V/Div
C2: PWM1_P driver signal 5.0 V/Div

Secondary Vds_Q3 versus Vgs_Q3 at 40 A
C1: Vds_Q3 5.0 V/Div
C2: Vgs_Q3 5.0 V/Div

Secondary Vds_Q3 versus Vgs_Q3 at 40 A
C1: Vds_Q3 5.0 V/Div
C2: Vgs_Q3 5.0 V/Div

Testing and Results www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

4.2.4 IR Scan Thermal Gradient (With Fan Cooling)

Figure 16. 48-V Input at Full Load (1.0 V and 40 A)

LMG5200

VIN Capacitors

Multi-Layer PCB

Small Return Path
Minimizes Power Loop

Impedance

xxx
xxx

SW

VIN

PGND

Metal 3

PGND

Legend

Copyright © 2016, Texas Instruments Incorporated

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

5 Design Files

5.1 Schematics
To download the schematics, see the design files at PMP4497.

5.2 Bill of Materials
To download the bill of materials (BOM), see the design files at PMP4497.

5.3 PCB Layout Recommendations
High-switching speed is important in a high-efficiency design. Optimizing the PCB layout to minimize the
power loop impedance and parasitic inductance is a necessary measure to achieve the goal.

It is recommended to use a multilayer board. Power loop parasitic impedance should be minimized by
having the input capacitor return path (between VIN and PGND) directly underneath the first layer as
shown in the below Figure 17. Loop inductance is reduced due to inductance cancellation as the return
current is directly underneath and flowing in the opposite direction. The VCC capacitors and the bootstrap
capacitors are placed in the first layer and should be as close to the device as possible.

The AGND of LMG5200 should not be directly connected to PGND in order to avoid the PGND noise and
not to cause spurious switching events due to noise coupling to HI and LI signals. Reducing the
impedance and the inductances on the board and the PCB layout should comply with the clearance and
creepage distance requirements.

Figure 17. Multilayer Board Cross Section With Return Path Directly Underneath for Power Loop

Design Files www.ti.com

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LMG5200: 48 to 1 V or 40 A Single-Stage Converter Reference Design

Figure 18. LMG5200 Top Layer Placement

5.3.1 Layout Prints
To download the layer plots, see the design files at PMP4497.

5.4 Altium Project
To download the Altium project files, see the design files at PMP4497.

5.5 Gerber Files
To download the Gerber files, see the design files at PMP4497.

5.6 Assembly Drawings
To download the assembly drawings, see

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 20%)
:

• At this point, a base chess game in Unity is almost complete, with some behaviors (such as en-passant and castling) still currently in development. This following week, we will start the creation of the web app and finalize the base chess game in Unity, allowing us to start our ML/AI work.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Furthered development of base chess game in Unity

• Researched multiplayer play in Unity


Next week’s SMART goals:

• Finalize base Chess application in Unity (Robert).

• Set-up web application (Michael, Izabella).

• Start updating our report to reflect our recent work (Ali).


Action Plan (task responsibility, timing, help needed):

• Finalize the base chess game

• Begin development of web application

• Research our choice of algorithms for AI variants


Open Issues, Risks, Change Requests:

• Finalizing our basic chess game


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application

2/6

2/13

2/27

On schedule

Since the chess game has made progress, there will be a renewed focus on the web application alongside game development.

First Chess Game

2/6

2/20

2/27

Behind schedule

While we have made considerable progress, some things still need to be implemented.

Electrical Engineering homework help

Homework 1
SWE 312 – Spring 2022

Dr. Mohsen Denguir

Sunday, March 20th, 2022

Deadline: Sunday, March 27, 2022

The owner of a car dealership would like to create a software to automate a part of the
job. This is how he describes the way they operate:

We have eight salespeople. As the customers come in, they greet them and
ask them what kind of car they are looking for. We also buy and sell used
cars. The customer has three options: buy a car in stock, order (through
us) from the car manufacturer, or get a car transferred from another dealer
(e.g., when the customer wants a car similar to one in stock but in blue
instead of in red).
We have two lots for three categories: family cars and sport cars. We also
have “weekly specials” where a number of cars are offered with discount
prices. For those whose purchase exceeds 50,000 SAR, we offer them a
coupon that gives them a discount for a full year of monthly car washes.
Some customers are interested in used cars and some want to trade in their
old cars for new ones. Each buyer can trade in only one old car, but of course
can buy as many new cars as they wish. In fact, we have had customers that
come in and want to buy new small cars for two kids going off to college and
a new family car for the spouse. Whether new or old, each newly bought
car must be registered with the government traffic administration.
The salespeople work on a small salary, but most of their income is from the
commission that they earn by selling cars. There is an incentive program
that awards salespeople by higher commission percentages as they sell more:
5% commission for sales up to 100,000 SAR per month, 7% for sales be-
tween 100,000 and 200,000 SAR and 10% above that. The commission is
calculated weekly and is a percentage of their total sales including additional
features, extended warranties, etc.
We like to keep track of our salespeople’s performance and we choose a
”salesperson of the year” who receives a bonus.

1

1. Formulate the problem to be solved using the template seen during the lectures. The
problem must be different from the one seen as an example during the lectures.

2. Identify the stakeholders and the actors.

3. Draw a use case diagram (using a tool chosen by you).

2

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 5%)
:

• We have started to build out the first prototype. We have setup a Github repository for the Unity Chess game as well as the web application. We have also created mock-up designs for the chess piece assets in the game, as well as a design for the user interface of the web client. A simple web application architecture of Node.js server and Reactjs client have been setup. The programming for the chess game in Unity has started.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Created repositories for chess game and web application

• Learned more about Unity as well started to program the chess game

• Started to program the web server and web client

• Created design for web client

• Found some assets for chess game

• Learning languages for this project (C#, JavaScript)


Next week’s SMART goals:

• Setup WebGL and other packages (webpack, babel… etc) on the web application. (Michael ++ ??)

• Get sample of chess game running on web application (Michael, Izabella)

• Learn more about game development with Unity and C# (Michael, Ali, Izabella)

• Continue writing Chess application in Unity (Robert, Izabella).

• Begin design our UI for the website and assets (Izabella, Ali)


Action Plan (task responsibility, timing, help needed):

• Learn more about the languages and technologies we are going to be using and how they will fit together

• Get web application to run the game

• Start Design chess game UML diagram

• Start creating the base chess game

• Set up bi-weekly/weekly meeting time with advisor


Open Issues, Risks, Change Requests:

• Finalizing choices of technologies/frameworks that will be used in project


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application UI design

1/30

1/30

N/A

On schedule

Basic design of web app’s features is complete, specific details (color scheme & other minor details) will be changed throughout the semester

First prototype of web application

2/6

2/13

N/A

On schedule

Date pushed back a week

First Chess Game

2/6

2/20

N/A

On schedule

Date pushed back two weeks

Design graph of Architecture

2/6?

2/6

N/A

On schedule

We have a small design already made, and need to extrapolate

* Examples adapted from CREG 257/258 at Lehigh University

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 25%)
:

• Currently, we are still working on finishing the base chess game. We are finishing up win conditions as well as piece-movement. We have also started getting the web-application setup to host this base chess game. We have also started building out a visual GUI for the website. This week we plan on finishing the game and having the website ready for and or hosting the game.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Furthered development of base chess game in Unity

• Began developing the front-end interface for the web-application


Next week’s SMART goals:

• Finalize base Chess application in Unity (Robert).

• Continue working on web-application (Michael, Izabella).

• Start updating our report to reflect our recent work (Ali).


Action Plan (task responsibility, timing, help needed):

• Finalize the base chess game

• Continue front-end and back-end development for the web-application

• Write our progress to our report


Open Issues, Risks, Change Requests:

• Finalizing our basic chess game

• Setup webGL with react


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application

2/6

2/13

3/4

On schedule

Development has started in tandem with the chess application. We already a prototype, we will now begin iterating.

First Chess Game

2/6

2/20

3/4

Behind schedule

We are only missing a few pieces, currently movement and end condition checks

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 7%)
:

• All members have been working hard on learning and building Chess in Unity. Going with our plan from last week, we are focusing on implementing a working basic chess game, and then implementing the web app (and adding support for variants in our game). Robert has been further developing code for chess behavior/moves, making sure each piece moves correctly and the game follows the chess rules. Michael has been implementing a method for us to continuously change the FEN string, representing the board that will change as the game is played. Izabella has been implementing the C# process to interact with Stockfish itself via UCI commands, obtaining moves at each positional change.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Learned more about Unity as well as well as continued to make chess game

• All members have chess repo set up


Next week’s SMART goals:

• Learn more about game development with Unity and C# (Michael, Ali, Izabella)

• Continue writing Chess application in Unity (Robert, Izabella, Michael, Ali).


Action Plan (task responsibility, timing, help needed):

• Continue learning about Unity

• Continue creating the base chess game

· Connect chess game to Stockfish to obtain moves

· Implement all chess rules/moves

· Generate FEN string with each move, using it to redraw board


Open Issues, Risks, Change Requests:

• Finalizing our basic chess game and getting it working


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application

2/6

2/13

2/27

Off schedule

This is not a priority until the chess game is working

First Chess Game

2/6

2/20

N/A

On schedule

This date may be pushed back depending on what progress is made the following week, for now we retain the original date.

Design graph of Architecture

2/6?

2/6

N/A

On schedule

Design graph has been created, although depending on how development goes it could change throughout the semester

Electrical Engineering homework help


Project Status Summary (Percentage Complete: 65%)
:

• The base chess game is essentially complete, and the implementation for the AI is in progress, as well as embedding the game in the web application. From here, our main tasks are testing, adding new variants (via new point systems), updating report, and creating our presentation and poster.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Furthered development of chess AI in Unity

• Worked on WebGL build for website

• Worked on updating report to reflect our recent work


Next week’s SMART goals:

• Finalize base Chess application in Unity (Robert).

• Get a successful build of chess game in webGL, set up webGL and integrate a build of the game with the website. (Michael).

• Complete implementation of Alpha-Beta AI and add variants (Izabella).

• Start updating our report to reflect our recent work (Ali).

• Contribute to poster and presentation (Everyone).


Action Plan (task responsibility, timing, help needed):

• Make any adjustments to base game that are needed

• Get the website running a build of the game

• Continue development of point-based AI for variants and test it to adjust weights as needed

• Write our progress to our final report and begin our presentation and poster design


Open Issues, Risks, Change Requests:

• Finalizing our chess AI and testing it

• Connecting a WebGL build of the game to Javascript

• Creating poster and presentation


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

Web application

3/18

4/1

4/1

On

schedule

Game running web application

Chess Game

4/1

4/1

4/1

On schedule

Now adding AI to base game

Electrical Engineering homework help

A Regulated 48V-to-1V/100A 90.9%-Efficient
Hybrid Converter for POL Applications in Data

Centers and Telecommunication Systems
Ratul Das and Hanh-Phuc Le

Department of Electrical, Computer and Energy Engineering
University of Colorado, Boulder, Colorado

{ratul.das, hanhphuc}@colorado.edu

Abstract—This paper describes the topology, fundamental
operations, and key characteristics of a Dual-Phase Multi-
Inductor Hybrid (DP-MIH) Converter for Point of Load (POL)
telecommunication and data center applications. The circuit
topology employs a unique configuration of switched inductor
and capacitor pairs to achieve complete soft charging and native
voltage balancing of flying capacitors regardless of mismatches
and variations in capacitor and inductor values. The converter
topology and its operation are verified by a five-level DP-MIH
converter prototype capable of delivering maximum load of 100A
at 1V-5V regulated output voltages from a 48V input supply. It
achieves 90.9% peak efficiency and 440 w/in3 power density for
48V-to-1V conversion and 95.3% and 2200W/in3 for a 48V-to-5V
conversion.

Index Terms—Hybrid converter, complete soft-charging,
switched capacitor network.

I. INTRODUCTION

Monthly global mobile data traffic is expected to surpass
100 ExaBytes (EB) in 2023 from around 20 EB today, and
merely ~2 EB in 2013[1]. This exponential growth has put
a critical pressure on the telecommunication infrastructure,
particularly on the architecture of power supply and distribu-
tion for this massive need. The most challenging components
in the power distribution for telecom power delivery include
the point-of-load (POL) converters connected to the 48V
intermediate bus as shown in Fig. 1[2]. In designing 48-
V PoL converters, transformer-based topologies have been a
popular choice with ones that have achieved a good range of
efficiencies around ~90%[3] and up to 93.4% [4]. However,
to maintain this efficiency range these converters either use
a complicated control scheme or have a limited conversion
ratio range[5]. In addition, bulky transformers are not desir-
able for converters that require both high power density and
large conversion ratios in applications where isolation is not
necessary.

Considering stringent space and load constraints, non-
isolated hybrid DC-DC converter topologies have shown
promising results. Notable examples include the 48V-to-1V
converter reported in [6] aiming at high efficiency and high
power density and the 120V-to-0.9V converter in [7] demon-
strating extremely large direct conversion ratios. Employing
a dual-inductor hybrid (DIH) converter architecture, both
converters demonstrated high efficiencies in a moderate load

85-265 V
AC

~400V
DC

DC/DC
48V Intermediate Bus

POL
Conv.

POL
Conv.

3.3V 2.5V

POL
Conv.

1.xVTelecom Unit

~400V
DC

PSU

DC/DC
48V Intermediate Bus

POL
Conv.

POL
Conv.

3.3V 2.5V

POL
Conv.

1.xVTelecom Unit

~400V
DC

PSU

H
ig

h
-V

o
lta

g
e

B
u

s

AC/DC

DC Storage

Fig. 1. Telecom power distribution system with 48V POL converters

S5

S2

Vin

B

A

B

C0 ILoad

S1 A
C1

Vout

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

A

A

B

B

Fig. 2. Dual-Phase Multi-Inductor Hybrid (DP-MIH) Converter

range up to 20A. However, the need for a precise capaci-
tor sizing strategy in [7] or a split phase operation in [6]
creates undesirable design complexities that would in turn
limit performance at heavier loads. Related works preceding
these implementations include the Flying Capacitor Multi
Level (FCML) converter reported in [8], the Hybrid Dickson
converter in [9], [10], and the multiphase series capacitor
Buck converter in [11], [12]. These interesting approaches for
non-isolated POL converters still have various short-comings.
Particularly, the FCML converter needs a capacitor voltage
balancing circuit, the Hybrid Dickson converter requires a
split-phase control and published implementations of the series
capacitor Buck converter exhibits efficiency limited to ~90%

978-1-5386-8330-9/19/$31.00 ©2019 IEEE 1997

S5

S2

Vin

B

A

B

C0 ILoad

S1 A
C1

Vout

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

A

A

B

B

AB1

AB2

(a) State 1(Phase A)

S5

S2

Vin

B

A

B

S1 A
C1

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

C0 ILoad

Vout

A

A

B

B

BB1

BB2

(b) State 3 (Phase B)

S5

S2

Vin

B

A

B

S1 A
C1

!

!

C2

C3

!

L1

L2

L3

Vx1

Vx2

Vx3

Vx4

S6

S7S3

S8
S4

L4

C0 ILoad

Vout

A

A

B

B

(c) States 2 and 4

Fig. 3. Operating states of the DP-MIH converter

for a conventional 12V-to-1V conversion. The need for higher
efficiency is perhaps self-evident, but larger conversion ratio,
low output voltage, and extremely high output current are also
critical since they are directly related to the space overhead,
thermal managementand hence cost of the input bus distribu-
tion, and to enabling technology scaling of the load process.

In order to explore the boundaries of hybrid converter capa-
bilities, in this paper we introduce, analyze and demonstrate
a Dual-Phase Multi-Inductor Hybrid (DP-MIH) converter),
shown in Fig. 2. The DP-MIH converter is derived as a
continuation of work from the Dual Inductor Hybrid (DIH)
converters [7], [6], and leverages similarities to the series
capacitor Buck converter. Section II describes the converter
operation and key characteristics, including complete soft-
charging operations of all flying capacitors without any spe-
cific capacitor sizing or split phase control, inherent capability
of providing less voltage stress across switches and inductors,
and the benefits of natively balanced inductor currents. Section
IV presents experimental results that validate advantageous
characteristics in enabling a DP-MIH converter converter
prototype to support large conversation ratios from a 48V
input to 1V-5V output at a maximum current of 100 A, and a
maximum load of 500W. Section V concludes the paper.

II. OPERATION OF THE DP-MIH CONVERTER

The paper focuses on a four-level version of the DP-MIH
converter, ignoring the zero level. It is called a 4-to-1 DP-
MIH converter where four is the number of voltage divisions
created by the switched capacitor network. The converter
circuit is shown in Fig. 2. The converter employs three flying
capacitors, four output inductors, and eight switches. As shown
in Figs. 3 and 4, the converter is operated with 4 switching
states within a switching cycle TS where States 1 and 3
are also named energizing phases A and B, respectively. In
Fig. 3, red color represents the capacitors getting charged
while blue implies discharging. The charged inductors in Fig.
3 have the correspondingly matching color in the inductor

current waveforms of Fig. 4. The first three inductors and
flying capacitors form three inductor-capacitor pairs where
each capacitor Ci is directly connected to and soft-charged
by inductor Li in a charging phase, A or B. The last inductor
L4 only handles soft discharging for the capacitor C3. The
capacitors are open-circuited and inactive during States 2 and
4. Every inductor is charged in one energizing phase, A or B,
and discharges to the output during the other energizing phase
and in States 2 and 4. The converter operation converges to
a steady state as each capacitor gets equivalent charge and
discharge once in every cycle, leading to native capacitor
voltage balance and inductor current balance. Charge for each
capacitor comes from either input voltage source for C1 or
from a capacitor at an immediate higher level in case of

A B

iL1(t) iL2(t)

A

D D D D D

B A B
2 3 4 1 2 3 4 1 2 3 4

∆”#

∆”#

∆”#

1

VC2(t)

∆$%

∆”&'(

VC1(t)

∆$%
iL3(t) iL4(t)

TS

1State

D

Phase

vout(t)

)&'(
*

+”$,
*

-“$,
*
“$,
*

)&'(
*

VC3(t)

Fig. 4. Operational waveforms of the DP-MIH converter

1998

TABLE I
SWITCHING NODE VOLTAGES IN ENERGIZING STATES

Switching node voltages
State 1 (Phase A)

Switching node voltages
State 3 (Phase B)

Start End Start End
V x1(AB1)

Vin
4

+ 4VC
2

Vin
6

� 4VC
2

V x2(BB1)
Vin
4

+ 4VC Vin6 � 4VC
V x3(AB2)

Vin
4

+ 4VC Vin6 � 4VC V x4(BB2)
Vin
4

+ 4VC
2

Vin
6

� 4VC
2

C2 and C3. In other words, flying capacitors discharge to
their immediate lower-level capacitors and inductors except for
C3, which discharges directly to L4. Assuming small voltage
ripples in the capacitors and inductor volt-second balance, the
steady-state voltages for C1, C2, and C3 are found as 3Vin4 ,
2Vin
4

, and Vin
4

, respectively.As the result, the four inductors
L1�4 are switched by the same voltage swing of Vin4 at
switching nodes VX1�X4. Each inductor has a charging duty
cycle D, i.e. in Phase A or B, making the output voltage
Vout =

DVin
4

. This intuitive conversion ratio result implies
a straightforward duty cycle control, allowing for a simple
and efficient output voltage regulation. General expressions
for steady-state voltages at the output and across the flying
capacitors for an N-to-1 DP-MIH converter are given as:

Vout =
DVin
N

and VCk =
(N�k)Vin

N
where, k = 1, 2, …., N � 1

(1)

For the intended operation of the converter, while Phases A
and B need to stay non-overlapped, they are not required to
be evenly distributed in the switching cycle. In general, a
uniform distribution of interleaving phases is preferred since it
minimizes the output current and voltage ripples and enables
load transient improvements as similarly found in multi-phase
Buck converters.

III. NATIVE SOFT-CHARGING AND ANALYSIS OF
SWITCHING NODE VOLTAGES

Native Soft-charging Feature

The key reason why this DP-MIH converter converter can
achieve complete soft charging for all flying capacitors is
evident in its operation in which every capacitor is charged
or discharged by an inductor in series. No capacitor is shorted

D
S

P
C

on
ne

ct
io

n

V
ou

t
S

en
se

Output

Input

L2

L4

S1
S5

S2
S3
S4

S6

S7

S8

Remaining circuit components are at the bottom side

C1
C2
C3

Gate Driving
Circuits

2.
49

˝

3.495˝

Fig. 5. A five-level 100-W DP-MIH converter prototype

in parallel with another capacitor or a low impedance source,
and thus no capacitor hard charging. This beneficial soft
charging is achieved natively without any complicated split-
phase control [13], [6] or capacitor sizing strategy [7]. Native
soft charging is also achieved regardless of variations and
mismatches in flying capacitor values that are oftentimes un-
avoidable because of different bias voltages and manufacturing
tolerance.

Analysis of Switching Node Voltages

As described in the operation of the DP-MIH converter
in Section II, all inductors experience an average voltage
swing of Vin

4
and carries an equal average current of Iout

4
.

When charging and discharging the flying capacitors, this
inductor current generates a voltage ripple of 4VC across each
flying capacitor. In other words, the voltage across each flying
capacitor has the same swing of 4VC

2
in addition to its steady-

state average voltage. However, in the operation of converter
shown in Fig. 3, the charging branches, AB1, AB2, BB1, and BB2
in the two phases A and B have different number of capacitors,
i.e. one or two capacitors. Therefore, the voltage swings at the
switching nodes VX1-X4 have different values, as detailed in
Table I. Specifically, during the charging phase VX2 and VX3
experience twice the voltage ripple of VX1 and VX4, leading
to larger variations in the current slope L2 and L3 compared
with L1 and L4 during energizing phase. However, note that
if this 4VC is small compared with Vin4 , the difference in the
inductor currents is insignificant. In addition, regardless of this
small inductor current mismatch 1) each inductor still maintain
a steady periodic waveforms every cycle, and 2) the feature
of native soft-charging for all the flying capacitor described
above is preserved.

IV. EXPERIMENTAL RESULTS
In order to validate the converter operations and advanta-

geous characteristics, a DP-MIH converter prototype depicted

TABLE II
MAJOR COMPONENTS

Components Part information
S1,2,3,4 2xEPC2015c
S5,6,7,8 2xEPC2023
C1 5.8uF 100V TDK
C2 5uF 100V TDK
C3 4.3uF 100V TDK
L1�4 1uH Vishay

Isolators Si8423
Gate Drivers LM5114, LMG1205

1999

TABLE III
COMPARISON CHART

Characteristics DIHC
[6]

Series Capacitor
Buck[11]

DP-MIH converter
(This work)

Input voltage 40-54 V 12 V 48 V
Output voltage 1-2 V 0.6-1 V 1-5 V

Maximum load current 10 A 60 A 100 A
Maximum power 20 W 60 W 500 W
Number of levels 7 5 5

Capacitor sizing and split
phase control

Required Not required Not required

Peak efficiency 93% @ 1V/4A 90.3% @ 1V/15A 90.9% @ 1V/30A

Fig. 6. Measured waveforms of the DP-MIH converter in a 48V-to-2V/15A
conversion

in Fig. 5 was implemented. The key components used in the
design are listed in Table II. Steady-state waveforms of the
four inductor currents, three flying capacitor voltages, and the
output voltage are shown in Fig. 6, verifying the converter
operation as described in Section II. In these experimental
waveforms, the converter was operated at 167-kHz switching
frequency, converting a 48V input to a 2V output and 15A
load. This switching frequency was specifically chosen to cre-
ate large ripples on the flying capacitor voltages and inductor
currents for convenient measurements. The flying capacitor
voltage waveforms in Figure 6 prove that soft charging is
achieved for all flying capacitors while the inductor current
waveforms demonstrates uniform current distribution for all
inductors. To obtain the efficiency in in Fig. 7, the converter
was operated at an optimal switching frequency of 333 kHz

Fig. 7. Measured efficiency of the DP-MIH converter operated at 333 kHz.

for voltage conversions from a 48V input supply to an output
regulated at 1V to 5V with a load current up to 100 A. The
converter achieves peak efficiencies of 90.9% for a 1V/30A
output, 93.6% for 2V/35A and 95.3% for 5V/40A. The ef-
ficiency measurements take into account all the powertrain
components as well as gate driving losses. Considering key
power conversion components, the converter achieves a power
density of 440 W/in3 at 1V and 2200 W/in3 at 5V and a current
density of 440 A/in3.

The DP-MIH converter converter prototype is compared
against previous works in Table III. Compared with the series
capacitor Buck converter [11], this DP-MIH converter con-
verter achieves a similar peak efficienciy for 1-V output while
supporting 4X conversion ratios, i.e. from 48V input instead of
12V, 1.6X maximum current capability, and 2X current at peak
efficiency. Compared with the DIH converter in [6],it achieves
10X maximum output current and 25X output power.

V. CONCLUSION

In this paper, a Dual-Phase Multi-Inductor Hybrid (DP-
MIH) converter was presented with operation analysis and

2000

experimental results. The converter exhibits a superior con-
figuration and performance at higher loads compared with the
state-of-the-art designs because of its unique hybrid topology
configuration and operation that enables complete native soft
charging in all flying capacitors without requiring any complex
control or capacitor sizing method. A 500-W experimental
prototype successfully demonstrates the intended operation
and characteristics, achieving 90.9% peak efficiency for a 48V-
to-1V conversion and regulating an output up to 5 V with loads
up to 100A.

ACKNOWLEDGMENT
This research work received financial and technical supports

from NSF ECCS program award No. 1810470, Oracle, Power
America, Lockheed Martin and the University of Colorado
Boulder.

REFERENCES
[1] R. Moller, “Ericsson Mobility Report November 2017,” Ericsson, Tech.

Rep.
[2] M. Salato, “Re-architecting 48v power systems with a novel non-isolated

bus converter,” in 2015 IEEE International Telecommunications Energy
Conference (INTELEC), Osaka, Japan, Oct. 2015, pp. 1–4.

[3] A. Kumar, S. Pervaiz, and K. K. Afridi, “Single-stage isolated 48v-
to-1.8v point-of-load converter utilizing an impedance control network
and integrated magnetic structures,” in 2017 IEEE 18th Workshop on
Control and Modeling for Power Electronics (COMPEL), Stanford, CA,
Jul. 2017, pp. 1–7.

[4] M. Ahmed, C. Fei, F. C. Lee, and Q. Li, “High-efficiency high-power-
density 48/1v sigma converter voltage regulator module,” in 2017 IEEE
Applied Power Electronics Conference and Exposition (APEC), Tampa,
FL, Mar. 2017, pp. 2207–2212.

[5] M. H. Ahmed, C. Fei, V. Li, F. C. Lee, and Q. Li, “Startup and control of
high efficiency 48/1v sigma converter,” in 2017 IEEE Energy Conversion
Congress and Exposition (ECCE), Cincinnati, OH, Oct. 2017, pp. 2010–
2016.

[6] G. S. Seo, R. Das, and H. P. Le, “A 95%-Efficient 48v-to-1v/10a VRM
Hybrid Converter Using Interleaved Dual Inductors,” in 2018 IEEE
Energy Conversion Congress and Exposition (ECCE), Portland, Oregon,
Sep. 2018.

[7] R. Das, G. S. Seo, and H. P. Le, “A 120v-to-1.8v 91.5%-Efficient 36-W
Dual-Inductor Hybrid Converter with Natural Soft-charging Operations
for Direct Extreme Conversion Ratios,” in 2018 IEEE Energy Conver-
sion Congress and Exposition (ECCE), Portland, Oregon, Sep. 2018.

[8] J. S. Rentmeister and J. T. Stauth, “A 48v:2v flying capacitor multi-
level converter using current-limit control for flying capacitor balance,”
in 2017 IEEE Applied Power Electronics Conference and Exposition
(APEC), Tamp, FL, Mar. 2017, pp. 367–372.

[9] Y. Lei, Z. Ye, and R. C. N. Pilawa-Podgurski, “A GaN-based 97%
efficient hybrid switched-capacitor converter with lossless regulation
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(ECCE), Montreal, QC, Sep. 2015, pp. 4264–4270.

[10] Y. Lei, R. May, and R. Pilawa-Podgurski, “Split-Phase Control: Achiev-
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Converter,” IEEE Transactions on Power Electronics, vol. 31, no. 1, pp.
770–782, Jan. 2016.

[11] K. Matsumoto, K. Nishijima, T. Sato, and T. Nabeshima, “A two-
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[12] P. S. Shenoy, M. Amaro, J. Morroni, and D. Freeman, “Comparison
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tions on Power Electronics, vol. 31, no. 10, pp. 7006–7015, Oct. 2016.

[13] Y. Lei, R. May, and R. Pilawa-Podgurski, “Split-Phase Control:
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Capacitor Converter,” IEEE Transactions on Power Electronics,
vol. 31, no. 1, pp. 770–782, Jan. 2016. [Online]. Available:
http://ieeexplore.ieee.org/document/7041205/

2001

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Electrical Engineering homework help


Project Status Summary (Percentage Complete: 40%)
:

• The base chess game is nearing completion. We are continuing to work on win logic as well as conditional movements. We are currently looking to embed the game for playing on a web application. Research has been done on how to deploy a web application to the world wide web. Next week, we are hoping to make considerable progress with our support for chess variants, the web application, and chess AI.


Lab Time and Accomplishments this week built on last week’s work

• No Lab Time this week.

• Furthered development of chess game in Unity

• Looked into methods for deploying web applications. Specifically, Digital Ocean and ansible.

• Further developed the web application architecture. Getting it ready for webGL build

• Built out plan for general AI algorithm


Next week’s SMART goals:

• Finalize Chess application in Unity, finalizing movement conditions and win conditions. (Robert).

• Continue working on web-application, get a successful build of chess game in webGL, setting up webGL and integrating a build of the game with the website. (Michael).

• Development of AI algorithm and points-based system for variants (Izabella).

• Start updating our report to reflect our recent work (Ali).


Action Plan (task responsibility, timing, help needed):

• Work on win conditions and movement conditions within unity.

• Get the website running a webGL build of the game. This build of the game can be incomplete.

• Begin development of point-based AI for variants and integrate it with already existing base game on Unity.

• Write our progress to our final report


Open Issues, Risks, Change Requests:

• Finalizing our chess game

• Setting webGL with react, connecting a webGL build of the game to javascript

• Multiplayer API for chess game

• Creating points-based AI system for variants


Milestones and Deliverables:

Milestones /

Deliverables

Planned Date

Forecasted Date

Actual Date

Status

Note

First prototype of web application

2/6

2/13

3/15

Behind

schedule

Barebones API that communicates with a front-end react client. This react-client has a webGL package. A build of the game is ready to be integrated

Second prototype of web application

3/18

4/1

4/1

On

schedule

Game running web application

First Chess Game

2/6

2/20

3/15

Behind schedule

We are only missing a few pieces, currently movement and end condition checks

Electrical Engineering homework help

Midterm 2, ECE 448- Spring 2022, UIC Name:

Page 1 of 4

Midterm 2, ECE 448 Transistors – Spring 2022
University of Illinois at Chicago

09:30 am to 10:45 am on March 14, 2022

Name: UIN:

1. [40 points] PROBLEM # 1

A pn junction has the doping profile sketched below. Throughout the problem assume the

carrier concentrations may be neglected (n=0, p=0) in the 0 ≤ x ≤ xi region of the diode.

a. What is the built-in voltage across the junction? Justify your answer

b. Invoking the depletion approximation, make a sketch of the charge density inside
the diode versus x.

c. Obtain an analytical solution for the electric field, E(x) at all points inside the
depletion regions (-xp ≤ x ≤ xn). Show all steps and also make a sketch of E(x).

Midterm 2, ECE 448- Spring 2022, UIC Name:

Page 2 of 4

d. Draw the energy band diagram for the diode under equilibrium conditions. Clearly

indicate x = 0 and x= xi points on your diagram.

2. [10 points] PROBLEM # 2
Establish a small-signal equivalent model for the common base configuration.
Provide a summary of all the device parameters.

Midterm 2, ECE 448- Spring 2022, UIC Name:

Page 3 of 4

3. [30 points] PROBLEM # 3

Given a npn BJT where IEn = 100 μA, IEp = 1 μA, ICn = 99 μA, and ICp = 0.1 μA, calculate:
a. αT

b. γ

c. IE, IC, IB

d. αdc

e. βdc

f. ICB0 and ICE0

Midterm 2, ECE 448- Spring 2022, UIC Name:

Page 4 of 4

4. [20 points] PROBLEM # 4

a. What is base-width modulation in a bipolar junction device? How can we reduce
the effects of base width modulation?

b. What is meant by graded base in a bipolar junction device? State any advantages

or disadvantages it reflects?

Electrical Engineering homework help

Version 1.0 Spring 2022 1

Lab 4: The Complete Microprocessor

Prerequisites: Before beginning this lab, you must:
• Understand how to use the tool flow (See the installation guide and Lab 0)
• Have completed Lab 1: Half Adder, Full Adder, 4-bit Incrementer and Adder.
• Have completed Lab 2: Multiplexers, Decoders, and the Arithmetic Logic Unit.
• Have completed Lab 3: Registers, Counters, and the “Brainless CPU”.

Equipment: Personal computer with the required software installed.
Files to copy from Lab 3 (do NOT copy from Lab 1 or Lab 2!):
alu.dig

and_add.dig

brainless.dig

four_bit_adder.dig

four_bit_mux.dig

four_bit_reg.dig

full_adder.dig

half_adder.dig

incrementer.dig

not_neg.dig

program_ctr.dig

program_ram.dig

two_bit_mux.dig

Files to download:
rom_vals.hex

ram_vals.hex

micro_top.v

micro_stim.v

Objectives: When you have completed this lab, you will be able to:
• Build a Memory Address Generator for a microprocessor.
• Design a ROM-based controller for a microprocessor.
• Create an instruction set for a microprocessor.
• Use the instruction set to write a program and enter it into a RAM.
• Execute programs in Digital and in Verilog.

Introduction
In this lab we will complete the microprocessor design by building a memory address generator

and a controller and adding them to your brainless microprocessor. We’ll also define an

instruction set for the controller. Finally, you will use the language inherent in your instruction

set to create a simple program, enter the program in your microprocessor’s memory and

execute the program. You will test the program first in Digital and then in Verilog.

Version 1.0 Spring 2022 2

Warning: Use the signal and circuit names provided! Verilog does not allow names to start
with a number or names that have dashes!

Create a folder named Lab4. Into that folder, copy the files listed above from Lab 3. Be sure to

only copy the required files. While it is tempting to do Lab 4 in the same directory where you

did a prior lab, it is advisable to start in a fresh directory in case something goes wrong. That

way, you still have the pristine prior lab results to copy again. In addition, this means that the

Lab4 folder will only have the files necessary for Lab 4.

Once you’ve copied the files from Lab 3, download the files provided for Lab 4 and place them

in the Lab4 folder. Now, you’re ready to start!

NOTE: You are required to design the circuits as presented in this document. Even though

Digital supplies many of the functions we will design, you are not to use them.

Task 4-1: Build and Test the Memory-Address-Generation Circuit
Now that your brainless microprocessor is working, we will add additional pieces of circuitry to

it and assemble the complete microprocessor. The first step is to modify the 4-bit incrementer

you built in Task 3-2 so that you can use it to generate the memory addresses for your CPU. The

memory address generation circuit is shown in Figure 1. The memory address generation circuit

is comprised of two independent pieces. One piece consists of a register and increment circuit,

which is your 4-bit incrementer, and is known as the Program Counter (PC). The other piece,

which accepts addresses from the data bus, is known as the Memory Address Register (MAR).

This register can be loaded from the data bus and holds the address of a storage location that

we want to access. This address does not have to be in sequence with the other addresses.

Thus, the MAR allows us to access a specific address and that address is usually obtained from

our RAM. In order to load the memory address from the data_bus to the MAR, we have an
enable signal that is called load_mar. The output of the address generation circuit is generated
by a mux, which controls whether the PC or MAR drives the address bus, addr_bus. The control
input to the mux, use_pc (short for Use Program Counter), is high when the PC values are
driving the address bus and low when the MAR contents are to be supplied to the address bus.

The memory address generation circuit will allow our processor to access memory locations

both in and out of sequential order. The circuit can:

• Automatically increment memory addresses after each instruction or operand is
retrieved by the CPU.

• Change the memory reference address so that we can store data to arbitrary memory
locations or read data from arbitrary memory locations.

Open Digital and select File->New and File->Save As and name the circuit addr_gen, making

sure it is saved in the Lab4 folder. Then build the circuit shown in Figure 1 using the circuits you

built in prior labs plus an inverter. Note that the data_bus input and the addr_bus output are 4-
bits wide. And remember to use the \ in front of underscores when entering the labels. For

Version 1.0 Spring 2022 3

example, data\_bus. You’ll also want to change the width of the program_ctr to 4. (Open the

program_ctr properties, select Open Circuit, then Edit->Circuit specific settings.) You may want

to label the MAR as “MAR” to remind you what this four-bit register is holding.

Figure 1. The Memory Address Generation circuit.

Notice the small triangle symbols labeled “pc” and “mar”. We’re going to add these to make

finding these wires easier when we simulate in Verilog. In Digital, this component is called a

Tunnel. In other environments, they are also referred to as connectors. The normal use case for

a Tunnel is to allow two distant points to be connected without requiring a wire to run between

them. That is, the Tunnel establishes a virtual connection. The advantage is that you can

connect distant things without your circuit becoming a mess of wires. In our case, we’ll use the

Tunnel components to give the wires names as there is no other way to do so in Digital.

The best way to add the Tunnel component is to add all the Tunnel instances you need and

name them before connecting them to the wires. Select Components->Wires->Tunnel and

place them as shown. Open their properties and set the net names as they appear in the

diagram. Finally, connect them to their respective wires.

When done, simulate the circuit in Digital. Does it work properly? Can you load values into the

Memory Address Register? Make sure that both the PC and the MAR can be used to drive the

Version 1.0 Spring 2022 4

addr_bus. Once you are convinced your circuit is working properly, end the simulation and save
your design. Take a screenshot of the circuit and paste it into your template.

Task 4-2: Build and Test the Controller Circuit
Remember the brainless microprocessor from Lab 3? How did it know how to execute each of

the instructions in our program? The answer, of course, is that we acted as the controller since

we knew how to set all of the signals to execute each operation. Next, we will design a

controller that will be able to automatically load instructions (in the form of hexadecimal

numbers, called operation codes or “opcodes”) stored in the Program RAM and then
automatically perform the operations needed to carry out each instruction. We will use a ROM

to decode the instructions and generate all control signals to operate the CPU. The only

remaining signals that we will control ourselves are clk, reset, and data_in.

The controller we will design and build is a ROM-based finite state machine as shown in Figure

2. Why do we need a finite state machine? It turns out that some of our operations cannot be

completed in one clock cycle. Think of the operation that writes the accumulator content to the

RAM at a specific address. We might need one or more extra clock cycles to accomplish this.

Rather than creating lots of opcodes for each individual step, our finite state machine allows us

to break down the opcodes into “micro-operations” or “micro-ops” (µ-ops). Each opcode, now
called macro-op, can have up to four micro-ops in our design. This will be enough for all of the

operations that we want to perform.

NOTE: The controller is shown here for reference. Instructions on building it come later.

Figure 2. The controller.

Version 1.0 Spring 2022 5

The central part of the controller circuit is the “Instruction ROM”. It performs “double duty”,

acting as both a decoder for the control signals and as the programmable logic for the finite-

state machine. The controller circuit consists of three pieces. One piece is a 4-bit register which

holds the current instruction, or opcode, we are currently executing. This is known as the

Instruction Register. The second piece is a 2-bit register which holds the number of the micro-

op we are executing. (If you recall, each instruction can be broken down into, at most, 4 micro-

ops numbered 0 to 3.) This 2-bit register is called the Step Register. The outputs of the two

registers form a 6-bit bus which is used as the address into the third piece, the ROM. A ROM is a

Read Only Memory into which we will preload values. Our microprocessor will be able to read

from the ROM but, as its name implies, the microprocessor will be unable to modify the ROM’s

contents.

Why use a ROM? Because it is a straightforward way to implement the logic that we need.

Otherwise, we’d have to generate 12 6-variable Karnaugh maps and implement the logic with

gates – not an attractive prospect!

As stated above, the output of the Instruction Register and the Step Register are combined to

form the address to the ROM. The 4 bits of the Instruction Register are on the left and the 2 bits

of the Step Register are on the right. This way, the steps of an instruction are contiguous in the

ROM. If we represent the addresses as hexadecimal numbers, that means the first instruction

will be contained in addresses 00, 01, 02, and 03. Then the second instruction will use

addresses 04, 05, 06. and 07. If the instruction doesn’t need all the steps, that’s ok – we can just

load the unused addresses with 0s.

There are two types of values which the ROM produces. Bits 1:0 are used to determine the next

value that will be in the Step Register. Bits 11:2 are all control bits. We used all but one of these

in the brainless CPU. The only new control signal is the one used to load a new instruction into

the Instruction Register.

The IR is loaded with an opcode that is stored in the Program RAM and appears on the Data

Bus. In order to load that opcode into the Instruction Register, the controller has to set its

load_ir output to 1. We call this operation the “Instruction fetch”. The “fetch state” will be the
first step executed for each of our instructions. The next three steps will be “execute states” to

achieve whatever functionality that instruction requires.

To build the controller, we’ll have to create a 2-bit register. To build this register, we’ll first have

to create a mux for 2-bit buses as shown in Figure 3. In Digital, select File->Open and select

four_bit_mux.dig. Immediately, select File->Save As and name the circuit two_bit_bus_mux.

IMORTANT: You must call this two_bit_bus_mux! If you leave out the “bus”, you’ll overwrite
the two_bit_mux circuit you created previously and your four_bit_mux will no longer work.
(If you already forgot the bus, that’s ok. Just copy the two_bit_mux circuit over from Lab 3
and start this step over.)

Version 1.0 Spring 2022 6

Figure 3. The mux for 2-bit buses.

Open the properties of the splitter/merger components and delete the “3-3,2-2,” leaving just

“1-1,0-0” and change the 4 to 2. This way, we’ll just have 2-bit buses rather than 4-bit buses.

Now delete the flip-flops no longer connected to the splitter/merger components. Now delete

the two_bit_mux components that are no longer connected as well as all the wires that are no

longer connected on both ends. Finally, change a, b, and y so that are 2 bits wide. Simulate this
circuit in Digital and, when you are satisfied that it works, save it. Take a screen shot and paste

it into your template.

Now we’ll finish the two-bit register as shown in Figure 4. Select File->Open and select

four_bit_reg.dig. Immediately, select File->Save As and name the circuit two_bit_reg. Open the
properties of the splitter/merger components and delete the “3-3,2-2,” leaving just “1-1,0-0”

and change the 4 to 2. This way, we’ll just have 2-bit buses rather than 4-bit buses. Now delete

the flip-flops that are no longer connected as well as all the wires that are no longer connected

on both ends. Finally, change d and q so that are 2 bits wide. Simulate this circuit in Digital and,
when you are satisfied that it works, save it and paste a screenshot of it into your template.

We now have the pieces we need to create the controller. In Digital, select File->New. Then

select File->Save As and save the new file as controller, again making sure it is saved in the Lab4

folder. Let’s start by placing the ROM. Select Components->Memory->ROM. You’ll notice the

ROM has two inputs. A is the address and sel is the output enable. If the output enable is 0, the
ROM outputs are not driven and, therefore, are at the high impedance, or Z state. To avoid

that, we’ll tie sel to the supply voltage.

Version 1.0 Spring 2022 7

Figure 4. The two-bit register.

Open the ROM properties and fill it out as shown in Figure 5. Then click on the Edit button in

the properties window and you’ll see a window as shown in Figure 6. At the top of that window

is the word File. Select File->Load and another window, shown in Figure 7 will appear. Select

rom_vals.hex, which you should have downloaded and placed in the Lab4 folder. Then click

Open. The ROM data window should now appear as shown in Figure 8. Click OK and OK to close

the ROM windows.

We’ll add three Tunnel components to this design. Remember to add the Tunnel components

and name them before connecting them to their respective wires. And don’t forget the \ in

front of the underscores when you set the Net name for each Tunnel.

Figure 5. The ROM bit definitions.

Version 1.0 Spring 2022 8

Figure 6. ROM data edit window.

Figure 7. Selecting the file with which to load the ROM.

Version 1.0 Spring 2022 9

Figure 8. The loaded ROM data.

Now place the four-bit and two-bit registers. Open their properties and select Open circuit. The

design will be a bit neater if we reorder the inputs. Select Edit->Order Inputs and match the

input order shown in Figure 2. Select Edit->Circuit specific settings and verify the width is 4. Do

this for both registers.

The last new work to do is to set up the splitter/mergers. Add the splitter/merger components.

Figure 9 shows how to combine the outputs from the registers. Figure 10 shows how to split

them back out. Why are we splitting them this way? The upper two bits coming out of the ROM

will be the next two bits to be loaded into the Step Register. So we’ll pull those off the bus and

route them internally. The next two bits are not currently used, so we’ll just leave them out.

The lower 10 bits will be the various control signals needed to operate the microprocessor.

We’ll discuss the contents of those bits shortly.

Figure 9. Combining the instr_reg and step_reg buses.

Version 1.0 Spring 2022 10

Figure 10. Splitting the ROM output.

Go ahead and add the inputs, the output, and all the wires. Remember that the data_bus input
is 4 bits wide and the control output is 10 bits wide.

Now, let’s discuss the contents of the ROM. Figure 11 shows the first 12 entries in the ROM.

Remember that the first line, “v2.0 raw” is something that Digital needs to properly read the

file. Note that the # character starts a comment so we can annotate the entries.

v2.0 raw

1205 # LOAD ACC; Load IR

0234 # Load ACC

0000 # unused

0000 # unused

1205 # ADD ACC; Load IR

0294 # ADD

0000 # unused

0000 # unused

1205 # STOP; Load IR

1000 # stay here

0000 # unused

0000 # unused

Figure 11. The first 12 entries of the ROM.

Since this is a hexadecimal file, each digit represents 4 bits. However, the left digit will only

represent the numbers 0-3, so there are only 14 bits per row. Bit 13 is on the left and bit 0 is on

the right. Table 1 defines what each of the bits represent. Because the first line of each

instruction is always 1205, that value has been entered for you. This shows how each

instruction will start on a multiple of 4 entries. Note that the very last row in the file, which isn’t

shown in the figure, is assigned the value 3FFF. This was done to force Digital to write out all

the entries of the ROM when exporting to Digital. You’ll see why this is needed in a later task.

Version 1.0 Spring 2022 11

Table 1. Bit definitions for ROM entries

Bit # Signal Name Function
13:12 next_step[1:0] The next step of this instruction to execute.
11:10 – These are unused. They are included so the next step bits align nicely

9 use_pc Propagate the Program Counter (PC) to the address bus and increment the
PC; otherwise select the Memory Address Register (MAR)

8 load_mar Load the MAR
7 arith One of the three controls for the ALU as defined in Lab 3
6 invert One of the three controls for the ALU as defined in Lab 3
5 pass One of the three controls for the ALU as defined in Lab 3
4 load_acc Load the accumulator.
3 acc_to_db Propagate the accumulator to the data bus; otherwise select the data mux

output
2 read The data mux should select the RAM output; otherwise it selects data_in
1 write Write the value on the data bus into the RAM.
0 load_ir Load the Instruction Register

Now that we know what the bits are, we assemble them into a value to place in the ROM. Take

the bits in Table 1 and arrange them horizontally as shown in Table 2. Note that each group of

four bits makes a hexadecimal digit.

Table 2. Bit Definitions Grouped in Hex Digits

name next_step unused use_pc load_mar arith invert pass load_acc acc_to_db read write load_ir
bits 13:12 11:10 9 8 7 6 5 4 3 2 1 0

Note that bits 11 and 10 are unused. It is a common practice when designing hardware to leave

unused bits in order to line things up nicely. Consider the first data line in Figure 11: 1205. It is

easy to see that this means the control output from the controller will be 205. On the other
hand, if we moved the next_step bits down to eliminate the unused bits, the first data line

would be 605. And if you’re trying to figure out if the output is correct, you’d have to think

about what that number would be without the top two bits. And that can, at times, become

painful since one sometimes forgets how many bits to ignore. Another advantage of leaving

some unused bits is that there’s room for enhancements. (Or bug fixes!)

So how does this work? When an instruction is in the instruction register, it combines with the

value in the step register to select a value from the ROM. This value divides into two functions.

The first function is to specify the next step in the instruction to execute. Since each instruction

has up to 4 steps associated with it, we need two bits dedicated to this task. These are bits 13

and 12. The second function is to control how the rest of the circuit is operating. These are the

10 bits 9 to 0.

How do you decide which values to assign in each step? The idea is to have the control signals

steer the data to where it needs to go and to get the various components to perform the

required logic. Let’s analyze the Load ACC command, step by step:

Version 1.0 Spring 2022 12

Step 0: This step is the same for all the instructions and is used to get an instruction from the
RAM to the instruction register. Table 3 is used to explain how each value was chosen. The bold

horizontal lines in the table separate the binary bits that form each hexadecimal digit.

Table 3. Step 0 of the Load ACC instruction.

Signal Name Value Discussion
next_step[1:0] 01 This takes us to the next step of the instruction.
unused bits 00 –
use_pc 1 Use the PC as the address to access the RAM and increment the PC
load_mar 0 Not loading the MAR
arith 0 Not doing an ALU function so default to 0
invert 0 Not doing an ALU function so default to 0
pass 0 Not doing an ALU function so default to 0
load_acc 0 Not loading the accumulator
acc_to_db 0 Need to propagate the data mux output to the data bus
read 1 The data mux should select the RAM output
write 0 Not writing to the RAM
load_ir 1 Load the value on the data bus into the instruction register

If you take these bits from top to bottom, you have 01_0010_0000_0101 in binary. (Recall

Table 2 where the bits are shown horizontally.) Converting that to hexadecimal, we get 1205,

the value we see in the rom_vals.hex file. Once this step is executed, we’re ready to move on to

step 1.

Step 1: This step will be similar for several of the instructions. In this case, all we are doing is
loading a value we are reading from the RAM into the accumulator. The values required are

shown in Table 4. Since this is the last step needed for this instruction, we’ll return to step 0 to

fetch the next instruction.

Table 4. Step 1 of the Load ACC instruction.

Signal Name Value Discussion
next_step[1:0] 00 This takes us back to step 0 so we can fetch the next instruction.
unused bits 00 –
use_pc 1 Use the PC as the address to access the RAM and increment the PC
load_mar 0 Not loading the MAR
arith 0 Not doing an ALU math function
invert 0 Not inverting
pass 1 Pass the value from the data bus to the ALU output
load_acc 1 Load the accumulator with the ALU output
acc_to_db 0 Need to propagate the data mux output to the data bus
read 1 The data mux should select the RAM output
write 0 Not writing to the RAM
load_ir 0 Not loading the instruction register

Version 1.0 Spring 2022 13

If you take these bits from top to bottom, you have 00_0010_0011_0100 in binary. Converting

that to hexadecimal, we get 0234, the value we see in the rom_vals.hex file. Once this step is

executed, we’re ready to move back to step 0.

Note that when each instruction completes, it returns to step 0 and fetches the next

instruction. This means that the next instruction actually starts on its step 1. Make sure this is

clear before proceeding.

Additional instructions are created in much the same way. At each step, you decide which

values to assign to the ROM entries to get the behavior you want.

The one strange instruction, STOP, is a bit different. Its step 1 simply stays in step 1 and all the

other bits are 0. That way, your design stays in a final, stable state so you can verify that the

circuit worked correctly.

Simulate the controller in Digital and satisfy yourself that it is working correctly. Be sure to save

it and take a screenshot of the circuit and paste it into your template.

Task 4-3: Build the Complete Microprocessor Circuit

Now it’s time to complete our microprocessor! Open Digital, if it isn’t already open, and select

File->New and then File->Save As and name the design microprocessor. Make sure it saves into

the Lab4 folder! Implement the microprocessor shown in Figure 12.

Version 1.0 Spring 2022 14

Figure 12. The completed microprocessor.

The circuit shown in Figure 12 is hierarchical. This means that the guts of the three large

modules are hidden from view. This makes connecting them much easier and has the added

benefit of a much simpler schematic. However, this does make it harder to see how all the

pieces work together. Therefore, another view of the completed microprocess is shown in

Figure 21 at the end of this lab.

Note that the subcircuit inputs have been reordered to make the wiring much simpler.

Remember to include the backslash when you label data_in and that both data_in and accum
are 4 bits wide.

Open the properties of the subcircuits and set the width of the controller to 7 and the width of

both the addr_gen and brainless subcircuits to 10.

Notice how the control bus is distributed. The programming for the splitters is shown in Figures

13-15. Note that you can resize the Splitter/Merger window to accommodate the number of

splits required in front of the brainless CPU.

Version 1.0 Spring 2022 15

Finally, we need to specify the RAM file to be loaded at startup. Select Edit->Circuit specific

settings and click on the Advanced tab. Select “Preload program memory at startup.” Then, on

the next line, click the 3 dots and navigate to your Lab4 folder and select the ram_vals.hex file

that you downloaded. Then click OK and save the design.

Figure 13. The splitter in front of addr_gen.

Figure 14. The splitter in front of the brainless CPU.

Figure 15. The splitter to extract load_ir.

Version 1.0 Spring 2022 16

Now we’ll simulate your design in Digital to see if the program we’ve provided works. First, let’s

have a look at the contents of ram_vals.hex shown in Figure 16.

v2.0 raw

0 # Load ACC

3 # value to load

1 # ADD ACC

5 # value to add

2 # STOP

Figure 16. The first 5 values in the ram_vals.hex file.

The first line in the file, v2.0 raw, makes it so Digital will properly load the file. Then we start an

actual program! The 0 is the instruction to load the accumulator with a value and the value to

load, 3, is on the next line. Following that is a 1, which is the ADD instruction, which adds the

next value, 5, to the value currently in the accumulator. Finally, 2 is the STOP instruction. If you

simulate digital using this file, you should see the following behavior:

When you start the simulation, the circuit will behave as if it’s been reset. To be certain, set the

reset to 1 and then back to 0 by clicking on it twice. The addr_bus and data_bus should both be
0, and the use_pc, read, and load_ir signals should all be 1. The circuit is ready to load an
instruction.

On the first positive edge of clk, which occurs when you click clk, the first instruction will be
loaded into the Instruction Register. You should see the addr_bus change to 1 and the
data_bus change to 3. In addition, the pass, load_acc, and read lines should all be 1. You’re
now ready to get the value of 3 into the accumulator. Click clk again so it returns to 0.

Now click clk so you get a second positive edge. The accum output should now be 3. In
addition, the addr_bus should be 2, the data_bus should be 1, and the use_pc, read, and
load_ir signals should be 1. We’re ready to load the next instruction. Click clk again so it returns
to 0.

Click clk to get a third positive edge. The accum output should still be 3. The addr_bus should
have changed to 3 resulting in the data_bus now being 5. The use_pc, read, arith, and load_acc
signals are all 1. Great – we’re ready to add the 5 to the 3 already in the accumulator. Click clk
again so it returns to 0.

Click clk to get a fourth positive edge. Success! The accum output is now 8 and the controller
has set things up to read the next instruction: use_pc, read, and load_ir are all 1. The addr_bus
is 4 and the data_bus is 2. Click clk again so it returns to 0.

Finally, click clk one more time to get a fifth positive edge. The accum output stays 8 and all of
the control signals are 0 because the STOP instruction has been loaded. Since use_pc is 0, the
addr_bus is now equal to the Memory Address Register. Since we’ve not loaded the MAR, it is

Version 1.0 Spring 2022 17

still 0 and so, too, is addr_bus. No matter how many more times you click on clk, nothing will
change. Figure 17 shows the final state of the circuit following the simulation.

Figure 17. The final state of the microprocessor following the first simulation.

Make sure you understand how the above simulation worked before proceeding as you’ll be

writing your own tests and implementing your own instructions in the next task.

The ram_vals.hex file contains another 11 lines of 0 which you can use as necessary in the next

task to build your own programs.

Once your simulation is working, take a screenshot showing the final values as shown in Figure

17 and paste it into your template. Then stop the simulation, save the design, and then select

File->Export->Export to Verilog. Make sure it saves to the Lab4 folder.

Version 1.0 Spring 2022 18

Task 4-4: Simulate the Design in Verilog

In order to simulate in Verilog, you’ll have to modify the RAM module as we did in Lab 3. Edit

microprocessor.v and find the code shown in Figure 18.

module DIG_RAMDualPort

#(

parameter Bits = 8,

parameter AddrBits = 4

)

(

input [(AddrBits-1):0] A,

input [(Bits-1):0] Di

Electrical Engineering homework help

Midterm 3, ECE 448- Spring 2022, UIC Name:

Page 1 of 3

Midterm 3, ECE 448 Transistors – Spring 2022
University of Illinois at Chicago

09:30 am to 10:45 am on April 11, 2022

Name: UIN:

Problem 1) A Schottky diode is made by depositing copper metal on n-type Silicon having doping
1016/cm3 at T= 300K. fM = 4.65 eV and c= 4.03 eV, Determine 40 pts.

a. fB
b. Vbi
c. W if applied voltage VA = 0
d. ú Eú max if VA = 0

Midterm 3, ECE 448- Spring 2022, UIC Name:

Page 2 of 3

Midterm 3, ECE 448- Spring 2022, UIC Name:

Page 3 of 3

Problem 3) What is meant by body effect and how threshold potential adjustments
are made with this method? 20 Pts.

Electrical Engineering homework help

Principles of Electrical Engineering II
332:222 Spring 2022

Project #2
Please submit to Canvas by April 15, 2022 at 11:59 PM

Project format

For all the projects assigned in this course the following format is to be used

1. Each project is to have a title page, which will include the student name at the top of the
page as well as their student ID number. The project number will be centered on the title
page along with the submission date. At the bottom of the title page please write “Principles
of Electrical Engineering II 332:222” and “Spring 2022.” The page format should be based on
8.5″ x 11″ (American A sized) plain white paper for all the pages in your report.

2. The title page will be followed by a brief introduction section, which will be one or two short
paragraphs long. After the introduction section the various project tasks will be answered.
Text must be typed. Schematic diagrams and graphs will be drafted and plotted using a
computer. Mathematical formulas may be neatly printed using either blue or black ink and
then scanned or typed using a word processor.

3. Class projects will be submitted to Canvas in PDF format. Please verify that your project
has been uploaded properly. Canvas has been set two allow 2, and only 2, submissions for
Project #2. The extra submission is just in case of internet connection issues. If you cannot
submit your project to Canvas and you have used up both of your submission attempts
immediately attach your Project #2, in pdf format, to an email and send it to Professor
McGarvey at johnmcg@soe.rutgers.edu and Head TA Yichao Yuan at yy470@rutgers.edu.

Project Description

An unmarked inductor, typically used in a switched mode power supply, is shown in the photo
below. For reference this component is about the size of a US quarter.

We want to find the inductance value of this component using basic electronic test
equipment which includes a function generator (an AC voltage source that can produce a
variety of waveforms over a wide range of voltages and frequencies), an oscilloscope (an
instrument that plots an input voltage versus time), a known capacitor, and various cables and
connectors. We also want to know the inductor’s internal resistance.

The circuit below was used to test the unknown inductor. A 200 Hz square wave with a
voltage that varies between 0 volts and 4.3 volts was supplied to the circuit using the function
generator. This acts as a repeating step input. Both the square wave input and the step
response were displayed using the oscilloscope. See the series of photos below. The input
square wave is the yellow trace and the step response is the blue trace. As you can see from
the oscilloscope photos the response is underdamped with minimal damping. The period of
the input square wave was selected to ensure that the response from the parallel LC circuit
had adequate time to settle to a steady-state value of zero volts before a new step input was
applied.

a) Use the approximation ω0≈ωn , for a lightly damped system, to find the value of the
inductor L. As can be seen from the oscilloscope measurements, the time period for five
cycles of oscillation is 195.5 μs.

b) Use the envelope data, from the last oscilloscope photo, to find the resistance in the RLC
parallel circuit. Note that this resistance will be frequency dependent due to the skin effect.
This resistance can be calculated based on the generic formula for the voltage response
v(t) = e−α t(C1 cos (ωn t)+C2 sin(ωnt)) where e

−αt represents the envelope of the voltage
response.

Note that finding the inductor resistance R requires going through a very difficult derivation
which I would consider beyond the scope of this course. For this reason, I have included the
formula that I derived for α below.

I have included the needed information below along with an extra “hint” as a present.

1. First, even though the test circuit looks simple, α is more complicated then the simple
series and parallel RLC cases that we studied in the lectures. The formula for α for this
test circuit is

α = 1
2 RsC

+
R

2 L

where

R = the unknown inductor internal wire resistance
Rs = 1050 Ω source resistance ( 1k Ω + 50Ω function generator resistance)
L = parallel inductance
C = parallel capacitance

The formula for α makes sense in that this test circuit has both series and parallel parts.
Inductors always have some internal resistance associated with them because the wire they
are wound with has some resistance depending on its size. Also, wire resistance is frequency
dependent due to something called the “skin effect” where the current flowing through a
conductor crowds to the outside at higher frequencies. The inductor resistance you will get is
at the RLC resonance frequency.

2. When you are calculating α you just want to look at the envelope of the waveform
which is represented by the e−α t term in the formula for the output voltage. The time
and voltage values for the two time points in the output voltage’s envelope are

At t1 vout = 188mV and t1 = 10 μ S
At t2 vout = 28mV and t2 = 400 μ S

I read these values off of the oscilloscope plot.

Hint: Divide the equation for the output voltage at t2 by the equation for the output
voltage at t1 to find α. Some algebra will be needed to get an equation to solve for alpha.

Electrical Engineering homework help

· The Systems Developed in Smart meters

· The Systems Developed in Theft detection

Paper Name

Summary

Contribution

Objectives

Methodology

Data collection tool

Outcomes

Gaps

1

A novel smart energy theft system (SETS) for IoT-based smart home.

Smart home networks are vulnerable to energy theft. Certain devices have to be installed to detect the attacks. An energy detection system that is based on statistical models and machine learning can be developed.

Developing an energy theft detection system to enhance the security of smart homes.

To propose a novel idea of Smart Energy Theft Systems for the smart home

The researchers reviewed the existing literature to determine how to reduce energy thefts. There was simulation of the smart energy theft system.

Literature review

An innovative smart energy theft system was developed for energy theft detection

The efficiency and effectiveness of the smart energy theft systems

2

Theft detection system using PIR sensor.

The implementation of a smart surveillance system by use of PIR and PR sensor can help improve home security. PIR detects the motion of objects. The PIR sensor is integrated with the camera to ensure that if there are movements in the room, the camera switches on. There is a mail system for providing the owner with a live stream of motion in the house. The smart home automation system can be used for theft detection

Developing a smart home automation system that can be used for theft detection

To implement a smart surveillance system by use of PIR and PR sensor for theft detection

Literature survey to determine how PIR sensors work and how they can be implemented. There was software implementation by use of Python and PR programming language

Literature review

Design of a smart surveillance system that can capture images and videos and send to a mobile phone

Information about limitations of the PIR sensors

3

Internet of Things Enabled Power Theft Detection and Smart Meter Monitoring System.

Power theft is an issue that concerns distribution companies. Smart meters with ICT can be used for detecting and alerting power theft. Internet of Things can be used in smart meter monitoring and power theft detection

Development of a system that detects power theft due to direct line hooking, meter tampering and meter bypass.

To reduce power theft in distribution companies

To develop an IoT enabled power theft detection system

The IoT enabled smart meter was designed with tampering detection circuit. An IoT server was developed by use of publish subscribe architecture, and an android application was designed by use of android studio 2.3

Online records

Prevention of theft by implementing an IoT enabled power theft detection system and smart meter monitoring system

How the linear-based approach detects power theft

4

Intrusion detection for cybersecurity of smart meters. 

The use of information communications technology enables real-time communication for smart meters. The infrastructures are; however, vulnerable to cyber-attacks. A two-stage cyber intrusion protection system is proposed for smart meters.

Proposal of a two-stage cyber intrusion protection system for smart meters.

To develop a system for protecting smart meters from cyber attacks

The researcher conducted research and proposed detection algorithms for detecting abnormal behaviours in smart meters. The support vector machine detection technique was used for analysing associated data for solving classification problems

Internet

Solving the cyber security vulnerabilities of smart meters

Effectiveness of the intrusion detection systems for smart meters.

5

Electricity theft detection in smart grid systems.

Electricity theft has severe consequences for the providers. Smart grids reduce the losses by using data analysis technique. Deep learning technique and machine learning can be used for identifying theft users.

Proposing an electricity theft detection system based on convolutional neural network (CNN) and long short-term memory (LSTM) architecture

To identity ways of reducing electricity theft

Electricity theft data was collected from a website. There was data pre-processing, training and testing of data. The proposed model was hyper tuned and the optimized model was evaluated.

Documents and records

Reduction of electricity theft in smart grid systems

Inefficiency of the model in identifying electricity theft users

6

Electricity theft detection using supervised learning techniques on smart meter data. 

The number of electricity thieves has been increasing. There is need to conduct research to detect electricity thieves accurately. A model based on real electricity data and machine learning technique can be developed to detect the electricity thieves.

Identification of electricity thieves using smart meter data.

To develop an electricity theft detection system on smart meters.

There was collection of electricity data. A proposed system model was developed. It included data pre-processing, data balancing, feature extraction, classification and validation. Simulations were conducted to show the performance of the models.

Online documents and records

Significant reduction in the number of electricity thieves

How utility companies can apply the models to identify electricity thieves

REFERENCES

1. Li, W., Logenthiran, T., Phan, V. T., & Woo, W. L. (2019). A novel smart energy theft system (SETS) for IoT-based smart home. IEEE Internet of Things Journal6(3), 5531-5539.

2. Jeffin, M. J., Madhu, G. M., Rao, A., Singh, G., & Vyjayanthi, C. (2020, July). Internet of Things Enabled Power Theft Detection and Smart Meter Monitoring System. In 2020 International Conference on Communication and Signal Processing (ICCSP) (pp. 0262-0267). IEEE. https://www.researchgate.net/profile/Madhu-G-M/publication/344056693_Internet_of_Things_Enabled_Power_Theft_Detection_and_Smart_Meter_Monitoring_System/links/5f589435a6fdcc9879d8d8bb/Internet-of-Things-Enabled-Power-Theft-Detection-and-Smart-Meter-Monitoring-System.pdf

3. Hasan, M., Toma, R. N., Nahid, A. A., Islam, M., & Kim, J. M. (2019). Electricity theft detection in smart grid systems: A CNN-LSTM based approach. Energies12(17), 3310.

4. Khan, Z. A., Adil, M., Javaid, N., Saqib, M. N., Shafiq, M., & Choi, J. G. (2020). Electricity theft detection using supervised learning techniques on smart meter data. Sustainability12(19), 8023.

5. Sun, C. C., Cardenas, D. J. S., Hahn, A., & Liu, C. C. (2020). Intrusion detection for cybersecurity of smart meters. IEEE Transactions on Smart Grid12(1), 612-622. https://e-tarjome.com/storage/panel/fileuploads/2021-01-04/1609777922_gh209.pdf

6. Saranu, P. N., Abirami, G., Sivakumar, S., Ramesh, K. M., Arul, U., & Seetha, J. (2018, February). Theft detection system using PIR sensor. In 2018 4th International Conference on Electrical Energy Systems (ICEES) (pp. 656-660). IEEE. https://d1wqtxts1xzle7.cloudfront.net/61618526/saranu201820191227-40729-19bavbh-with-cover-page-v2.pdf?Expires=1648390806&Signature=dM4f3NvuQhp~USFD28xCOPS~u56YYUBaq3gwRaMTUU9OwJInMFMHOwSJIjlWp6Z1Wp1O0R2S7Sm~5xxGH1KnYuFSaH7HOF7aG-DO9MaqtaUqvq1vVa8FrN~FHBx~GTDNHc8aLyUtbjPAhHh9gF1MTukXWp2FFn1-58D8qLE-rHA2NpET14wC4a18nUsFvpS1YuJ3iPxW8f7aPVV1dF~JpHiow9WWA0R1Dwvzp71Lku0vkNOtMeHEdSjZrvO35adj8LKixOpmi-uuJeOGw3cW-VTACad2rsFv9ARsNQYbWZx0Hs8G1L9hV1PeimO0~CReSsfnXNF~EF73LhyJNNqu~w__&Key-Pair-Id=APKAJLOHF5GGSLRBV4ZA

Electrical Engineering homework help

1. A single solar cell of area 1 cm2 has a photocurrent of 15 mA and a diode saturation current of 3.66 x 10-11 A at 300 K.  Calculate the open circuit voltage and the short circuit current of the solar cell.

2. Consider a silicon p-i-n photodiode with an intrinsic region of width 10 μm.  Light from a GaAs laser at energy ħω = 1.43 eV impinges on the diode.  The optical power is 1 W/cm2 . Calculate the photocurrent density in the detector.

3. At a wavelength of λ = 0.70 μm, the index of refraction for GaAs is n2 = 3.8 and that for GaP is n2 = 3.2. Consider a GaAs 1-x Pmaterial with a mole fraction = 0.40. Assuming the index of refraction is a linear function of the mole fraction, determine the reflection coefficient, R at the GaAs0.6P0.4 – air interface.

4. Consider a GaAs Fabry-Perot laser cavity.  The absorption loss in the cavity is given by an absorption coefficient of 20 cm-1.  Calculate the cavity length at which the absorption loss and the mirror loss becomes equal.

5. Consider the following materials,  GaAs, AlAs, GaP, AlAs and InAs,  Which material and combination of materials and alloys may be used for make photodetectors optimized in the following  two wavelengths;  0,5 to 0.8 μm, and 1.4 μm?

6. What material should be used for efficient detector or solar cell at 8 μm?

Electrical Engineering homework help

LA017995, Assignment 1, UEENEEE137A Ed1 1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

UEENEEE137A, Assignment 1

What you have to do
This assignment covers the material in topics 1, 7, 8 and 9 from the knowledge specification

KS01-EE137A of unit UEENEEE137A.

Answer in the space provided where possible but use separate paper if required. The

complete assignment will be returned to you so answering on the assignment allows more

easily understood feedback.

Brackets have been provided with multiple choice questions for you to insert the letter

corresponding to your answer.

For short answer questions keep your answers clear and concise and ensure you answer the

question as asked.

For diagrams also keep your answer clear and concise.

Your textbook will generally be the prime sources of information but don’t forget to access

the internet, OTEN readings and presentations.

This assignment is part of the assessment underpinning your workplace performance criteria;

therefore, you need to demonstrate that you have studied and comprehended these topics.

This will be shown by achieving 70% from your marker. If you do not achieve this then you

will be required to resubmit this assignment.

Total marks for this assignment is 70

2 LA017995, Assignment 1, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

Topics 1, 7, 8 and 9: Framework of WHS risk

Multiple-Choice questions, each question is worth 1 mark.

1 Work health and safety legislation in New South Wales has how many State regulators:

(a) One

(b) Two

(c) Three

(d) There is no state regulator as WHS is governed under a

Commonwealth Act since 2012. ( )

2 The WHS legislation revolves around:

(a) The WHS act and the WHS regulations.

(b) The WHS act and the WHS codes of practice.

(c) The WHS act and the WHS codes of practice and the WHS regulations.

(d) The WHS act managed by Safe Work Australia. ( )

3 Hazard means a situation or thing that has the potential to harm a person. Correctly select

the three steps to hazard control shown below.

(a) Identify the hazard, assess the risk, and make the change.

(b) Control the hazard, make the change, and eliminate the risk.

(c) Identify the risk, control the change, and make the hazard safe.

(d) the hazards, make the change, and document the risk. ( )

4 Mary’s boss observes Mary carrying flour and putting it into the dough mixing machine.

By doing this, Mary’s boss is in the first instance:

(a) Performing hazard identification by job analysis.

(b) Managing risk by observation.

(c) Introducing control measures into the workplace.

(d) Arranging more productive work practices for WHS. ( )

5 Avon services poker machines in clubs in New South Wales. Inside the clubs where

Avon services the poker machines there are many noisy inebriated patrons who often

scream abuse to Avon while he is working. This would be classed as:

(a) A work risk in his industry.

(b) A work hazard which is necessary with his job.

(c) A psychosocial hazard which could cause Avon harm.

(d) An environmentalwhich may need consultation. ( )

LA017995, Assignment 1, UEENEEE137A Ed1 3

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

6 When assessing the risks associated with any hazards the following applies:

(a) After identifying a hazard a risk assessment only needs to be done once because no

more risks would eventuate.

(b) Higher risk would be based on longer exposure to any hazard.

(c) Lower risk is always associated with the speed at which the operation needs to be

performed.

(d) With existing risk control measures in place risk is always a minimum. ( )

7 A risk assessment should be done when:

(a) A routine job is carried out that is often been done before.

(b) Changes at the workplace occur that may impact on the effectiveness of control

measures.

(c) The job safety analysis has shown negligible hazards.

(d) Be prescribed PPE is broken or damaged and needs to be replaced. ( )

8 The purpose of a risk analysis is to:

(a) Satisfy legislation so that the paperwork is all up to date.

(b) Identify significant risks and not spend time on the less significant risks.

(c) Define the relationship between the assessor and the environment.

(d) To exclude likely risks from further examination. ( )

9 Select from the answers below the answer which does not contain entirely engineering

control measures:

(a) Extraction fan, lighting, ergonomic seating, staff rotation

(b) Lighting, ergonomic seating, drink vending machine, extraction fan.

(c) Nonslip floor, powerful hand tools, coffee machine, industrial blower.

(d) ESD safe benchtop, padded chairs, coloured lights, music system. ( )

10 Any device or process which is implemented and automatically reduces risk thereafter is

called:

(a) Administrative control

(b) Isolation control

(c) Quality control

(d) Engineering control ( )

4 LA017995, Assignment 1, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

11 Vince is an apprentice electrician and has studied WHS at TAFE. His boss tells him to

go into the hot roof cavity and lay a cable from one end of the house to the other. Vince

discusses this with his boss and sought an alternative method to reduce risks to a

manageable level. This is an example of:

(a) Vince is lazy and takes the easy way out.

(b) Vince recognised the hazard and implemented engineering controls.

(c) Vince was able to eliminate the hazard and all possible risks associated with the

hazard.

(d) Vince used gap analysis to find the hazard and risks and then chose to use

administrative controls. ( )

12 Control processes must be reviewed when:

(a) All controls have been implemented

(b) An injury or incident occurs

(c) Data such as compensation claims suggest there is a problem

(d) All of the above ( )

Missing word questions, each question or part is worth 1 mark.

13 Risk is the possibility that _______________________might occur to people when

exposure to a hazard happens.

14 Risk action involves identifying the range of options for __________ risk and ________

those options and _________ a safe course of action plan and implementing it. (3 marks)

15 List the three factors that will be used to assess the level of risk: The sentences are started

for you, but you will need to find the answers in your textbook. (3 marks)

Step One: Consider how likely a risk _________________________________________

Step Two: Use the Risk Level Calculator to

____________________________________________________

Step Three: Identify and develop effective

__________________________________________________________.

Refer to Figure 2.3 in the Electrotechnology Practice textbook for the following 4 questions.

16 If in Step 1 of the risk and assessment control form, the activity is ‘drilling into a cavity

wall in a building and not knowing if there are any electrical cables behind that wall’ this

activity would represent a ______ risk rating.

17 Two electrical hazards that would be associated with this work are _________________

and _________________________________________. (2 marks)

LA017995, Assignment 1, UEENEEE137A Ed1 5

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

18 Two risk controls to be used in the activity of question 16 are ______________________

and ___________________________________________. (2 marks)

19 Two possible non-electrical hazards in the activity of question 16 are ______________

_________________and ____________________________. (2 marks)

20 Two hazards to be aware of when carrying out maintenance or breakdown electrical

work are _________________ and ____________________________. (2 marks)

21 WHS Regulations prohibit energized electrical work subject to certain exceptions. This is

an example of EL_ _ _ _ _ ________N.

22 The monitoring and review process is ON_____G.

23 Two examples of electrically actuated rotating, linear or reciprocating machines which

may form a hazard are _______________ and _____________________. (2 marks)

24 The associated risks from your two examples in Q23 are __________ and __________.

(2 marks)

6 LA017995, Assignment 1, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

Short answer questions, marks are as shown.

25 Consider the following list of hazards based on carrying a heavy roll of wire

down some damp stairs.

Match up the severity of the risk with each part. (risk level 1 is low; risk level 4 is

life threatening or permanent disability).

Select hazards and risks from the list below and populate the table with each

identifying number. (6 marks)

1 Slip hazard—twisted back or hernia.

2 Slip hazard from a lower step—torn ligaments in knee.

3 Wire too heavy—drop it and it rolls away, you grab it and cut your hand.

4 Bang head on beam above—brain injury, concussion.

5 Wire heavy, not trained in how to lift it—sprained shoulder.

Note that a particular hazard may have one or more possible risk levels.

A. Risk Level 1 B. Risk Level 2 C. Risk Level 3 D. Risk Level 4

If you need to elaborate, you may make small comments why you chose as you did.

LA017995, Assignment 1, UEENEEE137A Ed1 7

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

26 Match the 6 elements of the hierarchy of control with the order in which

they should be applied to mitigate risk. (6 marks)

Administrative control

Elimination

Engineering control

Isolation

PPE

Substitution

Use the following table to determine the risk level for the next 2 questions.

Very likely Likely Unlikely Highly unlikely

Life threatening High High High Medium

Detrimental High High Medium Medium

Harmful High Medium Medium Low

Negligible Medium Medium Low Low

Very likely Exposure to hazard likely to occur frequently.

Likely Exposure to hazard likely to occur but not frequently.

Unlikely Exposure to hazard unlikely to occur.

Very unlikely Exposure to hazard so unlikely that it can be assumed that it will not

happen.

8 LA017995, Assignment 1, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

27 Simon has been told to use a micrometer and

measure the size of some existing Single-strand

insulated copper wire protruding from a conduit

located under a dwelling with limited access. No

other information was given to Simon about these

pieces of cable or where they originate from, or in

fact if any circuit may potentially be live.

Identify likely hazards (high risk = 5, low risk = 1) and controls and complete the

table (the first one is done for you) (12 marks)

Hazard Controls to be Used No Control With Control

Energised conductors Test for voltage on the conductors. 5 1

LA017995, Assignment 1, UEENEEE137A Ed1 9

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

28 Here is a video link to YouTube:

https://www.youtube.com/watch?v=SuC4aurqkm8, confined space ‘Precious Time—The

Cody McNolty story’.

Watch the video and note the hazards and risks that arise.

Complete the table as you did for Question 27. Identify the hazards and risks in

getting equipment into a confined space. Match and select the risk criteria for

each event. (12 marks)

Potential Hazard Controls to be Used No Control With Control

.

Total marks = /70

Electrical Engineering homework help

Matlab Assignment (Individual)

This assignment is created as for the fulfillment of the Criterion 7 of ABET accreditation criteria.

Students should work alone for the following requirements.

Part 1.

(Highlighted “As a first example”)

a) Use Wz (power dissipated in the diode) to duplicate Fig – 28.

b) Draw density functions for Vs and Wz based on the problem descriptions

c) Use Matlab to evaluate E[Wz]

d) Use Matlab to find the Minimum R value.

Part 2.

(Highlighted “As another Example”)

a) Calculate R*(normal value of R), Rmin (Smallest R value), and Rmax (Largest R value).

b) Compute Probability Pc with (1) given Gaussian probability density function fR(r) and (2) standard normal distribution function φ(.). Compare your result.

Part 3.

(Highlighted “The third Example”)

a) Compute the quantity F(70) by using (2-54)

b) Draw the Rayleigh’s density function f(s) in Fig 2-31 by using (2-54)

c) Compute the conditional expectation E[S|S>70]

Everything should be typed!!! No handwritten, Photocopied, Camera-ed material is allowed.

Your Should include

1. Objective.

2. Screen shot of m file

3. Computation result

4. List of challenges that you had for the completion of the work – Explain the nature of challenges

5. List of topics in probability and statistics that you felt comfortable for this project.

6. List of topics in probability that you felt challenging for this project.

7. Conclusion

Electrical Engineering homework help

LA020088, Assignment 2, UEENEEE137A Ed1 1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

UEENEEE137A, Assignment 2

What you have to do
This assignment covers the material in topics 2, 3, 4, 5 and 6 from the knowledge

specification KS01-EE137A of unit UEENEEE137A.

Answer in the space provided where possible but use separate paper if required. The

complete assignment will be returned to you so answering on the assignment allows more

easily understood feedback.

Brackets have been provided with multiple choice questions for you to insert the letter

corresponding to your answer.

For short answer questions keep your answers clear and concise and ensure you answer the

question as asked.

For diagrams also keep your answer clear and concise.

Your textbook will generally be the prime sources of information but don’t forget to access

the internet, OTEN readings and presentations.

This assignment is part of the assessment underpinning your workplace performance criteria;

therefore, you need to demonstrate that you have studied and comprehended these topics.

This will be shown by achieving 70% from your marker. If you do not achieve this then you

will be required to resubmit this assignment.

Total marks for this assignment is 67

2 LA020088, Assignment 2, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

Topic 2: Hazards, risks and control measures—construction

Short answer questions (1 mark per written part or as shown)

1 What type of control measure would a dust collection fan be (e.g. Elimination)?

________________________________________________________________

2 State the main reason why some older switchboard materials should not be cut or drilled

without precautions.

________________________________________________________________

3 Name a toxic gas which may build up in an enclosed tank.

________________________________________________________________

4 Name one type of work activity involving a certain wood type which is a dangerous

wood dust hazard.

________________________________________________________________

5 Where may an electrician be exposed to legionella bacterium?

________________________________________________________________

6 Describe a serious hazard when cutting and joining fibre optics.

________________________________________________________________

7 Name 2 locations in some cottage type premises where asbestos can be found. (2 marks)

________________________________________________________________

________________________________________________________________

8 Name 2 essential types of PPE which should be issued to workers for their protection

when working in a bright sunny location at a building site. (2 marks)

________________________________________________________________

________________________________________________________________

9 A sign displayed on a construction site which shows a person’s head with ear protection

means that it is mandatory/not mandatory to wear the protection (Circle the correct

answer)

10 75dB of continuous noise in a workplace is the threshold of where permanent damage

can occur.

True or False (Circle the correct answer)

LA020088, Assignment 2, UEENEEE137A Ed1 3

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

11 The low reach insulated elevated work platform would be an ideal item of plant

equipment to use on live wires at the point of connection to a commercial building The

elevated work platform in NSW requires a high risk license from Workcover NSW to use

it.

True or False (Circle the correct answer)

12 Name one location that would be classed as a confined space by Workcover NSW.

________________________________________________________________

________________________________________________________________

13 What do the letters MSDS stand for?

________________________________________________________________

Total marks /15

4 LA020088, Assignment 2, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

Topics 3 and 5: Extra Low Voltage and Low Voltage Hazards and
Risks

Short answer questions (1 mark per written part or as shown)

Extra low voltage is defined as not more than 50Vac or 120Vdc. Low voltage is defined as

being between 50Vac and 1000Vac or between 120Vdc and 1500Vdc.

Be very careful of these names which could be misleading to a person who has not had

training in the Electrotechnology field. Low voltage is lethal. Extra low voltage could also be

lethal in the right environment such as high humidity, dampness, salt water, body salts from

perspiration etc. This is a very important area for safety risk management, and you must do

all the reading and show a high understanding of the dangers and hazards when working with

electrical circuits.

Read the following code of practice as your life and that of others around you is not

worth taking risks with electricity. Just copy and paste in GOOGLE.

http://wwwworkcovernswgovau/formspublications/publications/
Documents/low_voltage_electrical_work_code_of_practice_0964pdf

Watch the following video from YouTube

http://wwwyoutubecom/watch?v=HaSeu7-YG1M: the girl with hairdryer and

electrical worker…’Electrical Accident ‘It’s All About The Hair’

This video is about Low Voltage electrical hazard and lockout/tag out procedures.

Note that the consequences in Australia would be more severe due to the voltage and

frequency of our supply compared to the USA.

For questions 14 and 15 you must read the document from Safe Work Australia, ’Managing

Electrical Risks in the Workplace’ and use the information you learn from that document to

best answer them.

http://wwwsafeworkaustraliagovau/sites/SWA/about/Publications/
Documents/699/Managing%20Electrical%20Risks%20in%20the%20
Workplacepdf

14 From Section 51 of the above document, state the safe work procedure which

must be done when working on all electrical equipment or installations. Also,

state whether the electrical contractor in the video appeared to perform this

procedure. (3 marks)

________________________________________________________________

________________________________________________________________

________________________________________________________________

LA020088, Assignment 2, UEENEEE137A Ed1 5

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

15 From Section 6 of the Safe Work Australia document, discuss what the electrical

contractor in the video did not do, and show clearly 4 steps he should have taken

to comply with the Section 6 requirements. (5 marks)

________________________________________________________________

________________________________________________________________

________________________________________________________________

________________________________________________________________

________________________________________________________________

16 Place numbers from 1 to 7 in the blanks indicating the correct order of steps to be

taken in lockout/tag out. (7 marks)

Order of
action

Steps to be taken

Isolate equipment

Verify isolation

Control stored energy

Shut down equipment

Prepare for shutdown

Apply lockout/tag out devices

17 You know the equipment is safe when the power has been turned off.

True or False (circle correct answer)

18 Which of the following would be part of “control of stored energy”? Circle the

identifying letter. (4 marks)

(a) closing valves,

(b) locking out feeders,

(c) turning off power,

(d) releasing hydraulic pressure,

(e) releasing steam pressure,

(f) blocking movement of parts,

(g) releasing spring tension

6 LA020088, Assignment 2, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

19 Locks should be removed only by the person who installed them.

True or False (circle correct answer)

20 Name 2 items used to indicate that electrical work is being carried out. (2 marks)

________________________________________________________________

________________________________________________________________

Questions 21 to 24 refer to the computer power supply shown below.

ATX power supply interior

Legend

A—bridge rectifier

B—input filter capacitors

between B and C—Heatsink of high-voltage

transistors

C—transformer

between C and D—Heatsink of low-voltage,

high-current rectifiers

D—output filter coil

E—output filter capacitors

21 Charged capacitors in the power supply are only 12 Volts and do not represent a hazard.

True or False (circle correct)

22 If the 5 Volt output on the power supply is going into a low resistance load there is no

possibility of a fire hazard.

True or False (circle correct)

23 If you are required to service extra low voltage 5 Volt systems like this, there is no

hazard from wearing metal jewelry.

True or False (circle correct)

Nameplate for computer power supply

LA020088, Assignment 2, UEENEEE137A Ed1 7

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

24 The power supply is an extra low class of supply, having voltages as shown from

3.3 Volts up to 12 Volts This supply is quite safe for consumers to open and do

modifications with and represents no 230 Volt electrocution risk.

True or False (circle correct)

25 As a first year apprentice it is quite ok for your supervisor to leave you unsupervised to

install a new socket-outlet in an installation as you have done it by yourself on other

occasions.

True or False (circle correct)

Total marks /28

8 LA020088, Assignment 2, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

Topic 4: Hazards, risks and control measures associated with high
voltage

Multiple choice questions, 1 mark each

26 The dielectric strength of mica can be expected to be more than:

(a) 500 kV/mm

(b) 1500 kV/mm

(c) 2500 kV/mm

(d) 3500 kV/mm ( )

27 All of the following dielectric materials are preferred for high frequency applications

except:

(a) Polyethylene

(b) Butyl rubber

(c) Teflon

(d) Polystyrene ( )

28 The phenomenon of corona is generally accompanied by:

(a) a bang

(b) a hissing sound

(c) magnetic hum

(d) all of the above ( )

29 Surge voltage originates in power systems due to:

(a) lightning

(b) switching operations

(c) faults

(d) any of the above. ( )

30 Surge diverters are:

(a) nonlinear resistors in series with spark gaps to act as fast switches

(b) arc quenching devices

(c) shunt reactors to limit voltage due to the Ferranti effect

(d) over voltages of power frequency harmonics. ( )

LA020088, Assignment 2, UEENEEE137A Ed1 9

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

31 Step potential means:

(a) A step-up transformer is used to increase potential to a circuit in high

demand situations

(b) An earth fault situation has occurred and if the soil is high resistance a

workers legs will conduct current better than the soil in the distance of 1 step

(c) Voltages to domestic dwellings are stepped up as the cables run down a street to

overcome losses

(d) Rings of voltage radiating through damp soil can give rise to large

currents and voltages which would not be lethal when stepped upon. ( )

32 An authorised and properly trained person can be within __________ of energised 33kV:

(a) 2000mm

(b) 3000mm

(c) 700mm

(d) none of the above as the line would need to be de-energised. ( )

33 Induced voltage is:

(a) Voltage produced by the secondary of a high voltage transformer

(b) Due to the significant electromagnetic fields present around energized

HV electric lines, voltages may be induced onto adjacent de- energised or

non-commissioned electric lines

(c) Electrified fences work on the principle of electromagnetic induction and because

of the field of energy around the conducting wires, animals stay away

(d) Voltage which is sufficient to overcome rated creepage distances and then

cause surges in domestic installation. ( )

34 To eliminate electrical tracking between two close conductors, designers must provide

adequate CR______E distance between electrical elements.

Total marks /9

10 LA020088, Assignment 2, UEENEEE137A Ed1

© New South Wales Technical and Further Education Commission, 2015 (TAFE NSW – WSI), Version 1, September 2015

Topic 6 Hazards and Risks with harmful materials

Short answer questions (1 mark per written part or as shown)

35 Name the illness which is caused by Manganese in Welding Fumes.

________________________________________________________________

36 Welding with stainless steel can be hazardous due to: (2 marks)

________________________________________________________________

________________________________________________________________

37 Heating or cutting metal or other material which has been coated with lead will

produce a hazard. Describe the hazard and state what part of the body is affected

by this. (2 marks)

________________________________________________________________

________________________________________________________________

38 You have been told to blow the dust out of some electrical equipment Name the single

most dangerous airborne contaminant from this process.

________________________________________________________________

39 Name an example of an administrative control measure with respect to operating a laser.

Think especially about a worksite and how to warn other people.

________________________________________________________________

40 Name what effect the dust from drilling into bricks or cement will have on the human

body.

________________________________________________________________

41 What is the main hazard that exists when trimming optic fibre with a sharp knife or

scalpel blade?

(the answer is not cutting your finger)

_________________________________________________________________

42 Fluorinated hydrocarbons may be present in common refrigerants and are harmful

if they enter the body via the breathing passages. Name the parts of the human

body that may be affected. (4 marks)

________________________________________________________________

43 Name 2 electrical items that may contain polychlorinated biphenyls (PCBs). (2 marks)

________________________________________________________________

________________________________________________________________

Total marks /15